1. Verification & Test Support for Safety Standards
Brokerage 2011
VeTeSS
Verification & Test Support for Safety Standards
Helen Finch – Infineon UK

2. VeTeSS Verification & Test Support for Safety Standards
Target: safety relevant, embedded Transport applications
Automotive (passenger & commercial), Rail, Avionics, Off-highway
Problem: Computational state of embedded systems can be disturbed by transient effects
EM and RF fields, ESD and voltage transients
Safety features are advocated by standards (redundancy, diversity)
BUT: How to prove robustness of implemented features?
Proposal: a “Common Platform” for proving the efficacy of safety features in embedded systems according to safety standards
Test platforms/methods/benchmarks...

3. VeTeSS Technological Innovation
Applicable to broader Embedded Systems level
Microcontroller including multicore
Interfaces to sensors/actuators (IOs + A/D + D/A) -> System level
Embedded S/W
Fault injection verification & test techniques – integrated approach
Safety (fault resilience) evaluation of design as integral part of development
Applicable throughout development cycle (specification, design, modeling, implementation, prototype; also operational?)
Applicable at (and between/across) different hierarchy levels
Results- and coverage-driven -> metrics
Core Work Packages
Simulation and emulation based verification
Formal verification and static analysis
Physical test, H/W verification platforms
Automation, fault analysis and characterisation, benchmarking, performance/integrity predictions
Case studies, demonstration and evaluation
Industrial Priority: System Design Methods & Tools
ASP1: Methods and processes for safety-relevant embedded systems

4. VeTeSS Market Innovation
Safety standards current and emerging
ISO26262 will soon be adopted as an International Standard.
Others already in place
No suitable fault injection methods for verification exist today
Validation and metrics derived from generic (silicon) failure rates
Not feasible to associate failures with specific safety design features
Benefits:
Introduce safety evaluation into mainstream design activity: find problems earlier
Increase robustness and quality of embedded devices/systems
Minimize risk of failure in expensive and time-consuming certification process
Reduce need for re-spins to address safety hazards in design

5. VeTeSS Next steps
Interest from ~25 organisations, 15 industrial, 11 countries :
UK – Infineon, Astrium
Germany – Delphi, TU Braunschweig, Fraunhofer IIS, NXP, TWT
Austria – AVL, CISC
France – CEA LIST, Magillem
Belgium – DSP Valley
Italy – CRF, FBK, Turin Poly,
Spain – ESI Tecnalia, SEPSA, Integrasys, UP madrid, Univ Seville, La Salle Univ
Denmark – Aalborg Univ,
Finland – Oulu Univ,
Sweden – Volvo, Halmstad, Malardalen,
Latvia – Riga Univ
Confirm scope – considering:
Architectural level – system, subsystem, S/W, devices
Applications areas + target standards
Phase – spec, development, prototyping, operational?
Check positioning wrt existing projects and new proposals (SafeCer, RECOMP, MBAT, CESAR)
Identify additional participants e.g. tool vendor(s), certif. agency, stds group
to all interested parties draft proposal structure based on brokerage inputs
Workshop early 2011

6. Thank you, Helen Finch (Infineon UK) helen.finch@infineon.com