1. LHC injection timing simulation
Proposal
4/20/2019
Jean-Claude Bau / Ioan Kozsar / Julian Lewis

2. Jean-Claude Bau / Ioan Kozsar / Julian Lewis
SMPV
Proposal
CTR
Hardware
Card
MTT P 2
BPF1
LHC cable
BPF2
LHC event
HIX.FW-CT
SEX.F-F1K-CT
CTR
SPS cable
Pulse SEX.F-F1K
Gated on Dest=TI2 or Dest=TI8)
Async. Extraction
External
condition
CBCM
CBCM veto
Test mode
BPF1 = Beam Present Flag ring 1
BPF2 = Beam Present Flag ring 2
Cbcm veto= veto when LHC has mastership
LTIM device
4/20/2019
Jean-Claude Bau / Ioan Kozsar / Julian Lewis

3. Jean-Claude Bau / Ioan Kozsar / Julian Lewis
Hardware card logic
SEX.F1-1K    
Test Mode
Async. Extraction
BPF1
BPF2
Cbcm veto
Output to MTT
P2 Connector 1 X
4/20/2019
Jean-Claude Bau / Ioan Kozsar / Julian Lewis

4. Jean-Claude Bau / Ioan Kozsar / Julian Lewis
Logic for testing LHC injection
Test mode:
This is a logic level controlled by the buttons on the CCC external conditions panel
CBCM Veto:
This is set by the CBCM when it sees the external condition “Test Mode”
In this state the TI8/TI2 and corresponding Dump dynamic destinations can not be sent
Async Extraction:
This is a pulse generated by an LTIM under control of an application program
All other entries are logic levels
BPF1 & BPF2
Beam present in either ring blocks the Async Extraction pulse from being generated
4/20/2019
Jean-Claude Bau / Ioan Kozsar / Julian Lewis