Advanced Digital Design

Advanced Digital Design
The Synchronous Design Paradigm A. Steininger Vienna University of Technology

© A. Steininger & M. Delvai / TU Vienna
Outline The Need for a Design Style The „ideal“ Method – Requirements The Fundamental Problem Synchronous Design as a Solution Timed Communication Model Pros & Cons of Synchronous Design Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger / TU Vienna
recall Why a Design Stlye? Skew is inevitable and unpredictable It causes inconsistent transient states Their logic evaluation causes glitches Glitches are harmful if converted to stable states Boolean Logic (very efficiently) operates on the digital abstraction, assuming continuous validity and consistency of signals In addition, a design style is needed to maintain these abstractions in the presence of skew Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Without a Design Style…
…combinational gates may, due to race conditions, receive contradictory signals „simultaneously“ on different inputs, hence create glitch or runt pulses that may be converted into erroneous stable states or even cause metastability in storage loops. These glitches, runts and/or manifestations of metastability may propagate, and they may be subject to „Byzantine“ inter- pretation, causing further erroneous states. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

A Fair Comparison Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that next. Alternatives must be evaluated very critically with respect to improvements concerning area („embedded“, „intelligent“, cost…) power (mobile devices, heat,…) performance (as always) designability (efficient design of complex sys.) verifiability (test & validation cost!) robustness (critical apps, higher fault rates,…) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Chip Design Crisis short time-to-market hard physical limits impede miniaturization power delivery problems designer productivity gap increasing transient fault rates hard physical limits impede speed-up excessive test complexity heat problems increasing NRE costs Do we need a new („revolutionary“) design approach? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Performance Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Performance Performance has been improved by Transistor scaling (technology) Architectrural advances (pipelines, caches, …) Parallelization The design style has remained unchanged ! Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Area Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The MOS Transistor n-channel enhancement FET contacts gate oxide n+ substrate W L T OX channel Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Vizualizing Miniaturization
n Transistors 1995 n Transistors 2000 n Transistors 2005 n Transistors 2010 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Power Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

This is no more true for tech-nology nodes below 100nm!
Scaling Theory Scaling technology by a scales… area by /a2 transistor current by 1/a transistor power by 1/a2 power density (pwr/area) by 1 This is no more true for tech-nology nodes below 100nm! Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Static Power Consumption
gate tunnel currents (currents over gate oxide)  grow exponentially for thinner oxide subthreshold currents (currents over „open“ transistor)  grow for lower threshold voltage leakage currents (currents over reverse biased junction)  can be decreased by SOI, e.g. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Dynamic Power Consumption
switching currents (loading parasitic capacitances) crowbar currents (imperfect stack switching) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Power Consumption Trends
processor power [W] 1000 100 dynamic 10 1 static 0.1 0.01 [Furuyama, DSD’06] 1960 1970 1980 1990 2000 2010 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Power Delivery Problems
need to deliver currents of many amps into chip extreme current density in bondings & power rails need to supply huge current spikes within ps parasitic inductances critical buffer capacitances required noise margins reduced Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Designability Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Time-to-market needs to be ever shorter rapidly changing standards „last minute“ availability of crucial components/specs exploit market opportunities being late causes tremendous loss of profit Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Productivity Gap log +59%/a (Moore) trans/chip trans/staff/time +21%/a t [ITRS] We cannot design as complex chips as we could manufacture need much better tool support need to go to higher abstraction levels need to combine pre-designed modules Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Verifyability Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Verification Need to make sure that implemen-tation matches specification: all desired functions available no undesired behavior 70% of time spent on verification Model-based approach: spec transformed into (high-level) model model properties formally verified model is implemented in HW & SW BUT: how check implementation vs. model?? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Test Test complexity rises with more than O(n2) with circuit complecity It will soon cost more to test a transistor than to manufacture it log € cost/trans test costs  const -29%/a t [ITRS] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Robustness Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Transient Faults …occur 10…100 times more often than permanent faults today …originate from storage elements being upset (directly or indirectly) …can only be caused by disturbances with an energy larger than that stored in the affected cell … are often caused by particle hits (single event upsets: SEUs) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fault Rate Predictions
energy stored in a storage element scales with feature size power supply energy distribution of particles is non-linear significantly more particles towards lower energy fault potential largely increases with every technology node Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fault Mitigation stopping miniaturization is not an option technology (materials, shielding,…) reduces fault rate per transistor but still overall increase per chip robust circuit design Several techniques applied, but Design style not changed system-level fault tolerance current solution, expensive Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

A First Summary An ideal design method … minimizes power consumption miminizes circuit overhead naturally supports composability naturally aids testability yields robust circuits yields fast circuits. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

What we actually need When can SNK use its input? When it is valid and consistent f(x) SRC SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Timed Comm. Model for details see: M. Delvai, A. Steininger. Solving the fundamental Problem of Digital Design – A Systematic Review of Design Methods, th Euromicro Conference on System Design, Dubrovnik 2006. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Capture Condition Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: tcons,x > tsnkrdy,x msnk > - Dsnktrg Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Issue Condition Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: tinvalid,x > tsafe,x msrc > - Dinvalid Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Control by Global Time Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Synchronous Concept
f(x) FF1 FF2 TClk Pure time domain solution: Use periodic clock edges to derive triggers for source and sink; determine period such that capture condition and issue condition are always fulfilled. Tclk so bemessen, dass F(x) einschwingen können und sicher den Wert angenommen haben. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Synchr. Timing Model How does the synchronous design fit into the timing model of global time? What is p ? What is j ? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Implications Clock Period TClk = Period p determined by static timing analysis Free choice of msrc :  capture condition Phase j = p (!) this implies that msrc = -(Dsnktrg + Dcons) still we must guarantee msrc > -Dinvalid (issue condition) Therefore it must hold that Dinvalid > Dsnktrg + Dcons This is not formally safe – but it works! (No freedom to choose!) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Benefits of Sync. Logic Simplicity improves productivity time is considered discrete (!) design on high level of abstraction transients are irrelevant, all considered states are clearly defined timing analysis separate, after design clear distinction between data & clock Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Benefits of Sync. Logic (2)
High implementation efficiency: one single control signal for the complete system! periodic clock is easy to generate single-rail data coding minimum number of transitions on the data rails clock also provides a time base Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Resume 1 Synchronous design does work billions of working designs Synchronous design is VERY efficient wrt. design wrt. Implementation (area) So everything is solved Is it? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall The Original Problem When can SNK use its input? When it is valid and consistent f(x) SRC SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall What have we done? We have expressed a simple information related condition by means of complicated timing related parameters that we don‘t even know! DOES IT MATTER ? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

That damned traffic light
YES! It does matter Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

That damned … Traffic light number of waiting cars Microwave oven temperature of the food Wiper visibility through the front shield Stairway light presence of a person in the stairway Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

What‘s wrong? Events define important points in time. BUT: in practice the occurrence of an event cannot a priori be precisely predicted in time! There are many sources of uncertainty. As time is easy to measure, a projection is often made for the relative time between the occurrence of an event in the past and one expected in the future – instead of directly observing the latter. This becomes annoying when this artificial relation between actual event and time model is too weak (projection too fuzzy). Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Pre-Determined Timing
Designer User ?(unknown) projected conditions actual conditions worst case system model ?(imperfections) actual system safety margins Timing completely fixed after design No way to react to actual conditions & system Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Synchronous Approach
f(x) FF1 FF2 Relating flow control to time in this way is convenient and effective, but in fact the implied relation does not (naturally) exist! We need to establish this relation artificially during design (timing optimization & constraints) and preserve it during operation (temp, VCC) => „contract“ between designer, fab and user TClk Tclk so bemessen, dass F(x) einschwingen können und sicher den Wert angenommen haben. „After some TIME Tclk FF2 can use f(x)‘s output and at the same time FF1 can apply a new input“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The annoying consequences
need to determine clock period circuit functionality is technology dependent considerable design efforts, large design loops need to make worst-case assumptions necessarily pessimistic (corner cases) still no robustness wrt. exceeding them need to maintain global synchrony clock distribution problems (skew!) power consumption problems Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Timing Analysis not possible before the end of the design flow (large iteration loops!) Specification Design-Entry Synth. & Technol.-Mapping gate delays Partitioning & Placement interconnect delays Routing P-variations Manufact. Operation VT-variations Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Worst-Case Assumptions
normally too pessimistic real, chip could run faster no tolerance when exceeded graceful degradation desirable alim H(a) a Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Clock Skew Problem What happens if we move SRC time against SNK time? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Sync. Design – Properties
Area: + single rail encoding, single clock line - clock network Power: + small, efficient circuit - clock net., permanent concurrent switching Performance: + pure feed-forward flow control - worst case design, safety margins Designability: + good abstraction level for logic - timing analysis complex, composability? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Robustness metastability Issues clock = single point of failure non-redundant signal coding no graceful degradation timing margins help masking faults but they are shrinking! synchrony is a very strong assumption  it takes a lot of efforts to maintain it  „assumption coverage“ is lower Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Experimental Results Fault Injection Results for SPEAR [Thesis Rahbaran] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fault Masking Effects electrical masking too short fault pulse is filtered out by (parasitic) low-passes logical masking faults on masked gate inputs are irrelevant temporal masking signal values are considered only shortly before/during latching window; faults go unrecognized when outside Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Testability Scan test turns sequential problem into combinational one => hard to beat! Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conclusion An analysis of the data transfer process allows mapping the trigger conditions for data source and sink to the time domain, yielding an „issue condition“ and a „capture condition“. This convenient solution is used by some design styles, in particular the synchronous design. This mapping is, however, not natural. As an alternative signal coding may be used to control the triggers of source and sink. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conclusion Synchronous design is extremely efficient wrt. design and testing. It establishes a relation between handshake events and time that becomes increasingly cumbersome. Weak points are inherent robustness and composability Power efficiency, area efficiency and performance efficiency are very good in principle, but limitations in clock distributions tend to foil these benefits. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

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