Presentation is loading. Please wait.

Presentation is loading. Please wait.

Finite State Machine for Control

Published byΞένη Χατζηιωάννου Modified over 5 years ago

Similar presentations

Presentation on theme: "Finite State Machine for Control"— Presentation transcript:

1 Finite State Machine for Control
Implementation: Datapath Control Logic Instruction Register Opcode Field lec_03a_extra

2 PLA Implementation If I picked a horizontal or vertical line could you explain it? Op5 Op4 Op3 Op2 Op1 Op0 State3 State2 State1 State0 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource1 PCSource0 ALUop1 ALUop0 ALUsrce1 ALUsrce0 ALUsrce RegWrite RegDst NextState3 NextState2 NextState1 NextState0

3 PLA Implementation Red color shows lines that are "high" or "1"
Orange dots are AND gates Red color shows lines that are "high" or "1" Op5 = 1 Op4 = 0 Op3 = 0 Op2 = 0 Op1 = 1 Op0 = 0 State3 = 0 State2 = 0 State1 = 0 State0 = 1 Grey dots are OR gates, 1 or hi-Z "1" Output PCWrite = 0 PCWriteCond = 0 IorD = 0 MemRead = 0 MemWrite = 0 IRWrite = 0 MemtoReg = 0 PCSource1 = 0 PCSource0 = 0 ALUop1 = 0 ALUop0 = 0 ALUsrce1 =1 ALUsrce0 = 1 ALUsrce = 0 RegWrite = 0 RegDst = 0 NextState3 = 0 NextState2 = 0 NextState1 = 1 NextState0 = 0 State 1 (0001) is followed by state 2 (0010) if Op = with ALUsrce0 and ALUsrce1 set to "1" (true).

Download ppt "Finite State Machine for Control"

Similar presentations

Another Implementation Style

Another Implementation Style
Pipeline Example: cycle 1 lw R10,9(R1) sub R11,R2, R3 and R12,R4, R5 or R13,R6, R7.

Pipeline Example: cycle 1 lw R10,9(R1) sub R11,R2, R3 and R12,R4, R5 or R13,R6, R7.
Microprocessor Design Multi-cycle Datapath Nia S. Bradley Vijay.

Microprocessor Design Multi-cycle Datapath Nia S. Bradley Vijay.
{ CPU Design-Project CPU Design-Project Multicycle Datapath with Finite State Machine as Control Unit N.S.V Ravi Tej Uppu.

{ CPU Design-Project CPU Design-Project Multicycle Datapath with Finite State Machine as Control Unit N.S.V Ravi Tej Uppu.
Chapter 5 The Processor: Datapath and Control Basic MIPS Architecture Homework 2 due October 28 th. Project Designs due October 28 th. Project Reports.

Chapter 5 The Processor: Datapath and Control Basic MIPS Architecture Homework 2 due October 28 th. Project Designs due October 28 th. Project Reports.
1 5.5 A Multicycle Implementation A single memory unit is used for both instructions and data. There is a single ALU, rather than an ALU and two adders.

1 5.5 A Multicycle Implementation A single memory unit is used for both instructions and data. There is a single ALU, rather than an ALU and two adders.
CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicI: Building a Multicycle Data Path and a Control Path for a Microprocessor.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicI: Building a Multicycle Data Path and a Control Path for a Microprocessor.
EECE476 Lectures 10: Multi-cycle CPU Control Chapter 5: Section 5.5 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

EECE476 Lectures 10: Multi-cycle CPU Control Chapter 5: Section 5.5 The University of British ColumbiaEECE 476© 2005 Guy Lemieux.
Preparation for Midterm Binary Data Storage (integer, char, float pt) and Operations, Logic, Flip Flops, Switch Debouncing, Timing, Synchronous / Asynchronous.

Preparation for Midterm Binary Data Storage (integer, char, float pt) and Operations, Logic, Flip Flops, Switch Debouncing, Timing, Synchronous / Asynchronous.
ENEE350 Ankur Srivastava University of Maryland, College Park Based on Slides from Mary Jane Irwin ( www.cse.psu.edu/~mji )www.cse.psu.edu/~mji www.cse.psu.edu/~cg431.

ENEE350 Ankur Srivastava University of Maryland, College Park Based on Slides from Mary Jane Irwin ( )
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 313 - Computer Organization Multi-Cycle Processor.

Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Computer Organization Multi-Cycle Processor.
331 W10.1Spring 2005 14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 10 Building a Multi-Cycle Datapath [Adapted from Dave Patterson’s.

331 W10.1Spring :332:331 Computer Architecture and Assembly Language Spring 2005 Week 10 Building a Multi-Cycle Datapath [Adapted from Dave Patterson’s.
Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.

Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.
Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____.

Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____.
CMPE 421 Advanced Computer Architecture Supplementary material for Pipelining PART1.

CMPE 421 Advanced Computer Architecture Supplementary material for Pipelining PART1.
1 Computer Organization & Design Microcode for Control Sec. 5.7 (CDROM) Appendix C (CDROM) / 3055-05 / pdf / lec_3a_notes.pdf.

1 Computer Organization & Design Microcode for Control Sec. 5.7 (CDROM) Appendix C (CDROM) / / pdf / lec_3a_notes.pdf.
CPE232 Basic MIPS Architecture1 Computer Organization Multi-cycle Approach Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides

CPE232 Basic MIPS Architecture1 Computer Organization Multi-cycle Approach Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides
C HAPTER 5 T HE PROCESSOR : D ATAPATH AND C ONTROL M ULTICYCLE D ESIGN.

C HAPTER 5 T HE PROCESSOR : D ATAPATH AND C ONTROL M ULTICYCLE D ESIGN.
1 Processor: Datapath and Control Single cycle processor –Datapath and Control Multicycle processor –Datapath and Control Microprogramming –Vertical and.

1 Processor: Datapath and Control Single cycle processor –Datapath and Control Multicycle processor –Datapath and Control Microprogramming –Vertical and.
Multicycle Implementation

Multicycle Implementation

Similar presentations

Ads by Google