1. Program Phase Directed Dynamic Cache Way Reconfiguration
Subhasis Banerjee
Surendra G
S.K.Nandy
Presented by:
Xin Guan
Mar. 29, 2010

2. Outline Introduction to Program Phase Hardware Phase Detector
Cache Reconfiguration
Experiment Results

3. Outline Introduction to Program Phase Hardware Phase Detector
Cache Reconfiguration
Experiment Results 3

4. Program Phase What is Program Phase? How do we detect phases?
Informally, a phase is a period of execution whose characteristics are qualitatively different from those of the neighboring periods.
How do we detect phases?
Phase boundary
Instruction Stream (eg, certain code sections)
Data Stream (eg, data access pattern)
Asynchronous external events (eg, incoming message)

5. Program Phase
Mpeg2decode phase profile in terms of IPC (Instruction Per Clock), ROB (Reorder Buffer) occupancy, Issue Rate

6. Program Phase Conflict Miss Insufficient number of cache way
Program locality : generating conflict miss patterns
Increasing cache associativity does not gain much performance improvements in some cases, so reconfigure it to save power.

7. Outline Introduction to Program Phase Hardware Phase Detector
Cache Reconfiguration
Experiment Results 7

8. Hardware Phase Detector
Tag is used to identify the cache block during a conflict miss. Counter is used to get the number of times of conflict miss.
Counter Array
Cache
Sets 23

9. Hardware Phase Detector
Start to count at
the beginning
of every interval
Interval Vector
Cache
Sets #1 10
Normalization #2
Interval Vector #3 15 #4 #5 23 #6 14 #7 …… ……

10. Hardware Phase Detector
Clustering

11. Hardware Phase Detector
If the minimum distance d3 < threshold,
Clustering y d1 d3
Same cluster x d2

12. Hardware Phase Detector
Phase History Table
Every cluster corresponds
to a phase
Phase ID
Phase vector
Way Configurati on #1
Geometric centroid of cluster 1
2 way set associative #2
Geometric centroid of cluster 2
4 way set associative

13. Hardware Phase Detector
# of phases VS threshold
According to experiments, using threshold 1.1 most benchmarks exhibit 8 phases totally.

14. Outline Introduction to Program Phase Hardware Phase Detector
Cache Reconfiguration
Experiment Results 14

15. Phase Directed Reconfiguration
Way select signal enable/disable the pre-charge and sense amp
The phase is fed into cache controller, which decide the way configuration.
Architecture
Way select signal
Every 2 million instructions, the internal vector is calculated, and phase is found

16. Phase Directed Reconfiguration
Algorithm
If miss rate is low enough, shut down one way to save power
If miss rate is too high, enable one more way

17. Disabled Cache Ways Coherency 3 approaches.
Valid cache block should be accessible for future references.
Data residing in disabled cache ways should be coherent when the disabled cache way is enabled again.
3 approaches.
1.Flush the disabled way.
2.Fill buffer.
3.Victim buffer.

18. Disabled Cache Ways Fill Buffer x, y, z
Fill buffer can move the data in disabled way to enabled way, with several penalty cycles.
x, y, z

19. Disabled Cache Ways Victim Buffer x, y, z
Instead of moving data from disabled way to enabled way, the data can be stored in a victim buffer. This approach is adopted in this implementation.
x, y, z
Simple, avoid frequent activation of pre-charge and sense amplifier logic.

20. Outline Introduction to Program Phase Hardware Phase Detector
Cache Reconfiguration
Experiment Results 20

21. Experiment Results

22. Experiment Results

23. Experiment Results

24. Experiment Results
Average Saving of 32% of L1 data cache power with almost negligible loss of performance.

25. Conclusion Hardware Program Phase Detector
Dynamic Cache Reconfiguration
Saving average 32% power consumption with no performance degradation

26. Questions ?