1. ECE 352 Digital System Fundamentals
D Latches and Flip-Flops
In this presentation, we will look at two types of digital storage elements, the latch and the flip-flop.

2. Storage Elements
Many interesting types of circuits require keeping track of what happened in the past
Need to store some of this past information
Generally not storing everything that happened, just some key information
Example: Vending machine
Needs to track how much money was inserted
Doesn’t need to track which coins/bills were used
How can we store this data?
A combinational circuit’s output only depends on the current value of its inputs. However, for a lot of digital circuits, we also need to keep track of some information about what has happened in the past.
Usually, we don’t need to know everything that has happened, just the essential information for the task at hand. We use this information to make the circuit react to an input in different ways in different situations. For example, a vending machine needs to know how much money has been inserted, but not necessarily the exact mix of coins.
So, how can we store information in a digital circuit so that we can use it in the future?

3. What Does This Do?
Once we can get a value into this structure, it stays there as long as the circuit has power
Can hold a 1
Can hold a 0
In the structure shown, we have two inverters connected to each other in a loop. The two inverters reinforce each other, so whatever value is stored in this loop will stay there.
If Q happens to be equal to 1, then the top inverter outputs a 0, which is the input to the bottom inverter. The bottom inverter thus outputs a 1, so Q will stay a 1.
If Q happens to be equal to 0, then the top inverter outputs a 1, which makes the bottom inverter output a 0, so Q will stay a 0.
In this way, this structure can store either a 1 or a 0 as long as the circuit has power. But how can we get the 1 or 0 into it in the first place? 1 1
How do we get a value into this structure in the first place?

4. D Latch with Control
Want to control what goes into the storage element and when it happens
The bottom inverter is weak, and the tristate can overpower it without damage
This latch is level-sensitive: the value held in the latch can change whenever signal C is 1
Symbol
To make the circuit a useful storage device, we need to have a way to store a new value into it.
So, we add a tristate buffer that allows us to force the value stored in this structure to be whatever we want. Signal C is a control signal that enables the tristate buffer, and the value of signal D is what is written into the storage element when the tristate buffer is enabled. This type of storage element is called a latch. There are a few different types of latches; this one is called a D latch because when it is enabled, Q becomes equal to D.
Although it looks like the tristate buffer and the bottom inverter are in contention, we specifically design it so that the tristate buffer output overpowers the inverter output without damaging any part of the circuit. When the tristate buffer is enabled, the value at Q will be equal to D regardless of the output value of the weak inverter on the bottom. The output of the top inverter thus becomes /D, which then makes the bottom inverter output the same value as the tristate, ending the brief moment of contention.
We say that a latch is level-sensitive because the value it stores can be changed whenever input C is 1—it is sensitive to the logic level of the C signal. We also say that this particular type of latch is “transparent”, because while it is enabled, its output is equal to its input.
We represent the latch with the symbol shown here. There are other ways to implement a D latch, but they will all behave the same way.

5. Level-Sensitivity Problem
Consider a counter built with latches:
Stored value could update many times while C=1
The number of times it updates is unpredictable!
Update rate also depends on ambient temperature…
We want to update once per pulse on signal C
We want deterministic behavior!
The fact that the latch can change value whenever C is 1 makes it difficult to use in many of the circuits that require storage elements. For example, here is a counter circuit to keep track of how many times something happens. It adds 1 to the stored value whenever C is 1.
Unfortunately, while C is 1, we cannot control how many times we will increment the stored value. The number of times the latches will update is unpredictable, and depends on many factors – including how warm the circuit is. Obviously, this is not a very useful circuit for counting something.
What we would instead like to happen is to have the storage elements update exactly one time for each pulse of C being 1. Then we can actually control this counter.

6. Clock Signal
Need ability to make circuits where the storage elements only change at a pre-determined rate
A clock is a special signal that oscillates between value of 1 and 0 at a specific frequency
Controls how often the storage elements can update
(“positive” edge)
(“negative” edge)
We’ll use a special signal to control when our storage elements can update. We call this special signal a clock. It oscillates between 1 and 0 at a fixed rate, or frequency. A complete oscillation is called a cycle. Frequency is expressed in units of Hertz, where the number of Hertz is equal to the number of cycles per second. When the clock transitions from 0 to 1, we call that a rising edge, or more commonly, a positive edge. The transition from 1 to 0 is called a negative, or falling, edge.

7. D Flip-Flop
Build a “flip-flop” (FF) by connecting two latches together in Master-Slave organization
The output of the below flip-flop only changes on the negative edge of the control signal (the clock)
Master
Slave
Symbol
We can create a storage element called a D flip-flop that, unlike a latch, will only update once per clock cycle.
We connect two latches in a master-slave configuration. Notice that the control signals on the two latches are complements of each other, so only one latch is able to update at any given time. In this configuration, the output of the slave latch can only change on the negative edge of the clock signal. We’ll see why in a minute. We call this type of behavior “edge-sensitive”. It is sensitive to the edge of the clock.
We represent this D flip-flop with the symbol shown here. The triangle symbol indicates that the control input is edge-sensitive, and we add a bubble to show that it is negative-edge sensitive. We don’t need to label to this pin with a letter – we know that it is the clock input to the flip-flop.
“bubble” means negative-edge!

8. FF output Q changes on negative clock edge
Flip-Flop Waveform
The waveform demonstrates how the two latches work together to act as an edge-triggered FF
Colors on the waveform indicate which latch is enabled
FF output Q changes on negative clock edge
The master latch is only enabled when the slave cannot change.
The slave latch is only enabled when the master cannot change.
Two latches in a mater-slave configuration will display edge-sensitive behavior, and so will act as a flip-flop.
The key thing to notice here is that whenever the master latch can update, the slave latch holds its value, and vice versa. The waveform is color coded to indicate which latch is enabled in each phase of the clock cycle.
First let’s look at the output of the master latch in response to the input waveform. When we first apply power to the circuit at the start of the waveform, we don't know what value is stored in the master latch. We represent this with a dashed line between 1 and 0. The value in the latch must be a 1 or a 0, we just don’t know which. It becomes known when we first enable the latch. Whenever the clock signal is high (in the yellow parts of the waveform), the master latch is transparent and Q is a replica of D. When the clock signal is low, the master latch holds whatever value it had when the clock was last high.
Next let’s look at the output of the slave latch. The slave latch is only enabled when the clock signal is low, which is in the blue-green parts of the waveform. So, in the first interval, its output equals the output of the master latch, which was not known. When the clock signal goes high, the slave latch holds that unknown value. When the clock goes low again, the slave output can change, and takes on the value of the master latch output, which is now constant until the clock goes high again.
The end result is that the Q output of the flip-flop will only change at the negative edge of the clock, and it will take on the value of the D input immediately before that clock edge. Take a moment to look at the waveform to verify that it has this behavior.

9. Positive-Edge Triggering
A positive-edge triggered flip-flop can be constructed by adding an inverter
This changes which latch is enabled for the high vs. low phase of the clock
Master
Slave
Symbol
To create a flip-flop that responds to the positive edge of a clock, we add an inverter to the clock input. This changes which latch is enabled during each phase of the clock, and so the flip-flop responds to the opposite clock edge. The symbol does not have a bubble on the clock input, so we know that it is a positive-edge triggered flip-flop.
“no bubble” means positive-edge!

10. Flip-Flops and Timing Waveforms
In reality, there is some delay after the active clock edge before the FF input is stored and appears at the FF output
All real logic circuits have delay, and the flip-flop is no exception. There is always some small delay between the active clock edge arriving at the flip-flop and the flip-flop’s output changing.
Here we have two positive-edge triggered flip-flops connected so the output of one is directly connected to the D input of the other. These two flip-flops will receive the clock edge at exactly the same time, and at that time they each store the value on their respective D inputs. However, it takes a little time for that stored value to appear at their Q outputs. By the time that the output of the left flip-flop changes in response to the triggering clock edge, the right flip-flop has already stored its input – also at the triggering clock edge. It may seem clear when we show this timing waveform, but what about a functional waveform where we don’t show this delay?
Think about what happens if we let the flip-flop delay get smaller. No matter how small the delay is, the change to the flip-flop outputs is ALWAYS after the clock edge that causes them to store their inputs.

11. Flip-Flops and Functional Waveforms
The functional waveform does not show delay, but it still expresses causality
The value of a FF’s output just after the active clock edge is the value of its input just before that clock edge
In a functional waveform, the logic delays are assumed to be 0. However, the causality of the flip-flop must still be correctly observed so that the functional waveform is the same as the timing waveform, except for the delay.
A very simple way to think about this is that the output value of EVERY flip-flop immediately after the active clock edge is the value that was present on its D input immediately before that clock edge.
Even though the changes in B appear to be at the same instant as the clock edge that updated the flip-flop, they can’t affect the value being stored in the second flip-flop because the output change actually occurred AFTER the clock edge… it’s just that this delay is not shown on the functional waveform.
B’s changes do not show up at Y until the next clock edge!

12. Flip-Flop Direct Inputs
Sometimes we need a FF to hold a specific value immediately (before the next active clock edge)
An asynchronous input affects the flip-flop immediately, without requiring an active clock edge
A synchronous input has no effect unless the clock is at an active edge
Commonly used to force a circuit’s flip-flops into a known desired state on start-up
Direct set (preset) forces flip-flop to 1
Direct reset (clear) forces flip-flop to 0
Symbol
Often, we need a way to set the value in a flip-flop immediately after we power up the circuit, without waiting for the first active clock edge.
A flip-flop input that can immediately affect its value is called an asynchronous input. The inputs that only affect the flip-flop at an active clock edge are called synchronous inputs. The D input is a synchronous input, because its value is only stored into the flip-flop at times governed by the clock.
We normally use asynchronous flip-flop inputs to force the flip-flops in a circuit into a known state on start-up. Your computer needs this, for example, so it can always start execution at the same memory address. A direct set, or preset, input, forces the flip-flop to store a 1. A direct reset, or clear, input, forces the flip-flop to store a 0. Note that these signals don’t just temporarily override the output of the flip-flop, they change the value that is stored in the flip-flop.

13. Flip-Flops Direct Inputs In Quartus
The flip-flops available in Quartus have active-low preset (PRN) and clear (CLRN) inputs
PRN = 0 forces the FF to immediately store a 1
CLRN = 0 forces the FF to immediately store a 0
You need to tie these inputs to 1 (VCC) to disable them if you are not using them!
In Quartus, the flip-flops that you will use have active-low preset and clear inputs. If you don’t need these inputs, always tie them to 1 to disable them.
Remember, leaving an input disconnected is neither a 1 nor a 0!
Do NOT leave them unconnected!
D flip-flop with reset and disabled preset

14. ECE 352 Digital System Fundamentals
D Latches and Flip-Flops
This concludes our video on latches and flip-flops.