1. LAB 7

2. The address lines select one particular word
The address lines select one particular word. Each word in memory is assigned an identification number, called an address, starting from 0 up to 2k - 1, where k is the number of address lines.
memories vary greatly in size and may range from 1,024 words, requiring an address of 10 bits, to 232 words, requiring 32 address bits. It is customary to refer to the number of words (or bytes) in memory with one of the letters K (kilo), M (mega), and G (giga). K is equal to 210, M is equal to 220, and G is equal to 230. Thus, 64K = 216, 2M = 221, and 4G = 232.

3. Exercise 7.1
The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input–output data lines are needed in each case? (b) 2G * 8
(c)  2G x 32
(d)256K*64

4. Exercise 7.1
(b)  4M x 16
4M = 4×220 = 222, so 4M x 16 takes 22 address lines and 16 data lines, for a total of = 38 I/O lines.
(c)  2G x 32
2G = 2×230 = 21 ×230 = 231, so 2G x 32 takes 31 address lines and 32 data lines, for a total of 63 I/O lines.
(d)256Kx64=218 x64 A=18, D=64

5. Exercise 7.9
A DRAM chip uses two‐dimensional address multiplexing. It has 13 common address pins, with the row address having one bit more than the column address. What is the capacity of the memory?
= 25 address lines. Memory capacity = 225 words
The DRAM chip has 12 rows and 13 columns, for a total of 25 address lines. 225 memory locations.

6. Exercise 7.9
= 25 address lines. Memory capacity = 225 words

7. Exercise 7.14
It is necessary to formulate the Hamming code for four data bits, D3, D5, D6, and D7, together with three parity bits, P1, P2, and P4. (a)* Evaluate the 7‐bit composite code word for the data word 0010.
(b)  Evaluate three check bits, C4, C2, and C1, assuming no error.
(c)  Assume an error in bit D5 during writing into memory. Show how the error in the bit is detected and corrected.
(d)  Add parity bit P8 to include double‐error detection in the code. Assume that errors occurred in bits P2 and D5. Show how the double error is detected.

8. Exercise 7.14 1