1. Memory in PC
By Tien-Hsiang Lo

2. Introduction PC Architecture Memory Interface Architecture
DRAM INITIALIZATION SEQUENCE
Memory Sizing Flow
BANK/ROW ACTIVATION
CAS Latency
MEMORY INTERFACE GATED CLOCK
S3~suspend to RAM
Verilog code view
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3. PC Architecture (Laptop)
CPU
AGP Bus
VGA
Memory
North
Bridge
PCI Bus
CardBus
LAN
South Bridge
IDE
USB
Audio Modem
PCI-to-PCI
ISA Bus (LPC)
SMBus
PCI Bus
EEPROM可接在KBC or South Bridge下
Slot0
Slot1
DIMM SPD
EEPROM
(24C02)
CardBus
SIO
KBC
SMBus
SMBus
Battery
Thermal
Sensor
Slot0
Slot1
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4. Memory Interface Architecture
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5. DRAM INITIALIZATION SEQUENCE
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6. Memory Sizing Flow de
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7. BANK/ROW ACTIVATION
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8. Truth Table
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9. CAS Latency
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10. MEMORY INTERFACE GATED CLOCK
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11. MSEQ BLOCK DIAGRAM
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12. S3~Suspend to RAM
The S3 sleep state is a low wake-up latency sleeping state where all system context is lost except system memory. CPU, cache, and chipset context are lost in this state. Hardware maintains memory context and restores some CPU and L2 configuration context. control starts from the processor's reset vector after the wake-up event. (from ACPI spec)
1. Placing the memory into a low-power auto-refresh or self-refresh
state.
2. Devices that are maintaining memory isolating themselves from other
devices in the system.
3. Removing power from the system. At this point, only devices supporting memory are powered (possibly partially powered). The only clock running in the system is the RTC clock.
OS notify all of driver to save register and status…, enter power down mode, Enable Wakeup Event, SouthBridge receive S3 command, enter S3Zzzzz
Wakeup Event trigger (panel, mouse, power button…), BIOS execute to restore (program the initial boot configuration of CPU, restore the cache controller, restore memory controller, restore other devices, jump to the waking vector), OS resume q^__^p
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13. Access RAM 2019/2/27 Tien-Hsiang Lo Time scale 1ns/10ps
module acess_ram( RADDR, RCLK, RDATA, RENJ, WADDR, WCEJ, WCLK, WDATA );
output [2:0] RADDR;
output RCLK;
input [31:0] RDATA;
output RENJ;
output [2:0] WADDR;
output WCEJ, WCLK;
output [31:0] WDATA;
reg RSTJ;
reg [3:0] counter;
reg ck;
reg wej;
reg rej;
reg [31:0] dout;
parameter udly = 1;
/* --- Place Module Definition Here --- */
initial begin
RSTJ = 1'b0;
RSTJ = #23 1'b1;
ck = 1'b0;
forever #10 ck = ~ck;
end
assign WCEJ = wej;
assign RENJ = rej;
assign WDATA = dout;
assign WADDR = counter[2:0];
assign RADDR = counter[2:0];
assign WCLK = ck;
assign RCLK = ck;
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14. 2019/2/27 Tien-Hsiang Lo always @(posedge ck or negedge RSTJ)
if (!RSTJ)
counter <= #udly 4'h0;
else if ((!wej) || (!rej))
counter <= #udly counter + 1'h1;
wej <= #udly 1'b1;
else if (counter==4'h0)
wej <= #udly 1'b0;
else if (counter==4'h7)
rej <= #udly 1'b1;
rej <= #udly 1'b0;
else if (counter==4'hf)
case(counter[2:0])
3'h0 : dout = 32'h ;
3'h1 : dout = 32'h ;
3'h2 : dout = 32'h ;
3'h3 : dout = 32'h ;
3'h4 : dout = 32'h ;
3'h5 : dout = 32'h ;
3'h6 : dout = 32'h ;
3'h7 : dout = 32'h ;
endcase
// $display($time,," end now ");
// $finish(1);
endmodule // acess_ram
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15. Module Synchronous `timescale 1ns/10ps module sync_2psram( RADDR,
RENJ,
RCLK,
WADDR,
WCEJ,
WCLK,
WDATA,
RDATA );
input [2:0] RADDR;
input RENJ;
input RCLK;
input [2:0] WADDR;
input WCEJ;
input WCLK;
input [31:0] WDATA;
output [31:0] RDATA;
parameter udly = 1;
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16. sram for data through freq infx from WCLK domain to RCLK domain
reg [31:0] databuf [0:7];
reg [2:0] rdec;
reg [31:0] d0,d1,d2,d3;
reg [31:0] d4,d5,d6,d7;
reg [31:0] RDATA;
/******************************************************************************
sram for data through freq infx from WCLK domain to RCLK domain
*******************************************************************************/
always @(posedge WCLK)
if (!WCEJ) begin
databuf[WADDR] = WDATA;
end
always @(posedge RCLK )
if (!RENJ)
RDATA <= databuf[RADDR];
//rdec = RADDR;
/*******************************************************************************/
endmodule
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17. Combination module top_ram; wire [2:0] RADDR; wire [31:0] RDATA;
wire [31:0] WDATA;
wire [2:0] WADDR;
wire WCEJ;
wire WCLK;
wire RCLK;
wire RENJ;
acess_ram I_7 ( .RADDR(RADDR[2:0]), .RCLK(RCLK), .RDATA(RDATA[31:0]),
.RENJ(RENJ), .WADDR(WADDR[2:0]), .WCEJ(WCEJ), .WCLK(WCLK),
.WDATA(WDATA[31:0]) );
sync_2psram I_6 ( .RADDR(RADDR[2:0]), .RCLK(RCLK), .RDATA(RDATA[31:0]),
endmodule // top_ram
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18. Thank you ~Stressed backwards is Desserts.~