Presentation is loading. Please wait.

Presentation is loading. Please wait.

Status of Slave Board (SLB) ASIC

Similar presentations


Presentation on theme: "Status of Slave Board (SLB) ASIC"— Presentation transcript:

1 Status of Slave Board (SLB) ASIC
SLB ASIC (version 1) used in Slice Test 2001 has bugs in JTAG, Readout block (Parallel to Serial Converter: PSC). Timing instability of the long shift registers of PSC[218] and Control part (Mask[160] and Test Pulse[160]) Confliction of JTAG TDO data at the state transition from “shift” to “capture” DR due to timing problem Bug fixed version SLB ASIC (version 2) has been delivered in July,2002 and tested since then. 7/10/2002 TGC electronics meeting in CERN

2 Error phenomena Shift register problem Frame Prev. BC data
Current data Next data 2. JTAG state transition problem 7/10/2002 TGC electronics meeting in CERN

3 C.Fukunaga @ TGC electronics meeting in CERN
Cure for the bugs Introduction of Master-slave shift register structure A small logic to ensure c(apture)DR must come later than TCK 7/10/2002 TGC electronics meeting in CERN

4 C.Fukunaga @ TGC electronics meeting in CERN
Results 7/10/2002 TGC electronics meeting in CERN

5 C.Fukunaga @ TGC electronics meeting in CERN
Name Bit RW DEPTH 21 Depth of L1 Buffer TESTPULSE 5 Set delay of Test Pulse Trigger DELAY 4 Set delay of input SCHEME 1 Low : 3 out-of 4 , High : 4 out-of 4 L1VETO Low : through , High : L1A = 0 CLKINV Low : order , High : invert RESET Internal ECR & BCR DRDRST Derandomizer Reset DCVETO Low : DC balanced , High : Normal SEU RO SEU Flag MODULE 8 Indicate Module Type and Module Address OVERFLOW Indicate Derandomizer Overflow ID 32 ID= MASK1P 160 Mask Pattern for Readout and Matrix MASK1 Mask Enable for Readout and Matrix MASK2P Mask Pattern for Matrix only MASK2 Mask Enable for Matrix only TPP Test Pulse Pattern 7/10/2002 TGC electronics meeting in CERN

6 Summary for SLB ASIC version 2
Low-pT matrix part: Verification with 8000 patterns for each doublet/triplet and wire/strip. Readout part: PSC with new shift register scheme works fine, but we are still doing tests for this parts. Control part: All JTAG functions work fine. Mask and Test Pulse: Both work fine owing to new shift register structure. 7/10/2002 TGC electronics meeting in CERN


Download ppt "Status of Slave Board (SLB) ASIC"

Similar presentations


Ads by Google