1. Lecture 8: Verilog Examples
UCSD ECE 111
Prof. Farinaz Koushanfar
Fall 2017
UCSD ECE 111, Prof. Koushanfar, Fall'17

2. UCSD ECE 111, Prof. Koushanfar, Fall'17
Outline
Example 1: Vending machine
Example 2: Parking lot occupancy counter
Example 3: Datapath and control path
UCSD ECE 111, Prof. Koushanfar, Fall'17

3. Example 1: Vending Machine
Vending Machine: A soft drink dispenser
Accepts Nickel (¢5), Dime (¢10), and Quarter (¢25)
Dispenses a drink when receives ¢35
Returns change
Ref:
UCSD ECE 111, Prof. Koushanfar, Fall'17

4. Diagram Inputs and outputs Other units Drink- dispensing module
nickel_in
dispense
Coin-input module
Vending Machin module
dime_in
quarter_in
nickel_out
Change-dispensing module
dime_out
UCSD ECE 111, Prof. Koushanfar, Fall'17

5. UCSD ECE 111, Prof. Koushanfar, Fall'17
How many states?
Possible ways to pay for a drink:
5+5+…+5 = 35
= 35
25+10 = 35 …
UCSD ECE 111, Prof. Koushanfar, Fall'17

6. UCSD ECE 111, Prof. Koushanfar, Fall'17
Vending Machine
Let’s draw a Mealy FSM
The states represent sum of the inserted coins (do we need more?).
Start/¢0 ¢5
¢10
¢15
¢30
¢20
¢25
UCSD ECE 111, Prof. Koushanfar, Fall'17

7. UCSD ECE 111, Prof. Koushanfar, Fall'17
nickel_in
Idle/¢0
nickel_in ¢5
nickel_in
¢10
nickel_in
¢15
¢30
nickel_in
¢25
nickel_in
¢20
nickel_in
UCSD ECE 111, Prof. Koushanfar, Fall'17

8. UCSD ECE 111, Prof. Koushanfar, Fall'17
dime_in
dime_in
dime_in
Idle /¢0
nickel_in ¢5
nickel_in
¢10
nickel_in
¢15
dime_in
dime_in
¢30
nickel_in
¢25
nickel_in
¢20
nickel_in
dime_in
UCSD ECE 111, Prof. Koushanfar, Fall'17

9. UCSD ECE 111, Prof. Koushanfar, Fall'17
quarter_in
dime_in
dime_in
Idle /¢0
nickel_in ¢5
nickel_in
¢10
nickel_in
¢15
quarter_in
dime_in
quarter_in
dime_in
¢30
nickel_in
¢25
nickel_in
¢20
nickel_in
dime_in
UCSD ECE 111, Prof. Koushanfar, Fall'17

10. UCSD ECE 111, Prof. Koushanfar, Fall'17
Output
Output:
{dispense, nickel_out, dime_out}
E.g, output = 3’b110 (/110) means dispense and return a nickel.
UCSD ECE 111, Prof. Koushanfar, Fall'17

11. UCSD ECE 111, Prof. Koushanfar, Fall'17
Output/
quarter_in/100
dime_in
dime_in
Idle /¢0
nickel_in ¢5
nickel_in
¢10
nickel_in
¢15
quarter_in
dime_in
dime_in
quarter_in
nickel_in/100
¢30
nickel_in
¢25
nickel_in
¢20
nickel_in
dime_in/100
dime_in
UCSD ECE 111, Prof. Koushanfar, Fall'17

12. UCSD ECE 111, Prof. Koushanfar, Fall'17
Change Dime
Start/¢0 ¢5
¢10
¢15
dime_in/110
¢30
¢25
¢20
UCSD ECE 111, Prof. Koushanfar, Fall'17

13. UCSD ECE 111, Prof. Koushanfar, Fall'17
Change Quarter
quarter_in/110
Idle /¢0 ¢5
¢10
¢15
quarter_in/101
quarter_in/111
¢30
¢25
¢20
Ops! what about ¢30 with a quarter? =
We need one more state.
UCSD ECE 111, Prof. Koushanfar, Fall'17

14. UCSD ECE 111, Prof. Koushanfar, Fall'17
Owe ¢10
quarter_in/110
Idle /¢0 ¢5
¢10
¢15
quarter_in/101
/001
quarter_in/111
-¢10
¢30
¢25
¢20
quarter_in/101
In -¢10, we owe the user ¢10.
UCSD ECE 111, Prof. Koushanfar, Fall'17

15. Vending Machine Module
module vending_machine( input wire clk, rst, input wire dime_in, nickel_in, quarter_in output reg dispense, output reg dime_out, nickel_out ); endmodule
UCSD ECE 111, Prof. Koushanfar, Fall'17

16. UCSD ECE 111, Prof. Koushanfar, Fall'17
State Reg
module vending_machine( input wire clk, rst, input wire dime_in, nickel_in, quarter_in output reg dispense, output reg dime_out, nickel_out ); localparam IDLE=3’d0, FIVE=3’d1, TEN=3’d2, FIFTEEN=3’d3, TWENTY=3’d4, TWENTY_FIVE=3’d5, THIRTY=3’d6, OWE_TEN=3’d7; reg [2:0] ps, ns; // 3-bit present state and next state endmodule
UCSD ECE 111, Prof. Koushanfar, Fall'17

17. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM Template
begin // set all outputs to their inactive values. nickel_out=0; dime_out=0; dispense=0; ns = ps; // By default, we stay at the same state. case(ps) default: ns = IDLE; endcase end
This is the Verilog template for FSM.
UCSD ECE 111, Prof. Koushanfar, Fall'17

18. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM: case(ps)
ns = ps; // by default we stay at the same state. case(ps) IDLE: if(nickel_in) ns = FIVE; else if(dime_in) ns = TEN; else if(quarter_in) ns = TWENTY_FIVE; FIVE: if(nickel_in) ns = TEN; else if(dime_in) ns = FIFTEEN; else if(quarter_in) ns = THIRTY; TEN: if(nickel_in) ns = FIFTEEN; else if(dime_in) ns = TWENTY; else if(quarter_in) {ns, dispense} = {IDLE, 1’b1}; endcase
UCSD ECE 111, Prof. Koushanfar, Fall'17

19. UCSD ECE 111, Prof. Koushanfar, Fall'17
FIFTEEN and TWENTY
case(ps) FIFTEEN: if(nickel_in) ns = TWENTY; else if(dime_in) ns = TWENTY_FIVE; else if(quarter_in) begin {ns, dispense} = {IDLE, 1’b1}; nickel_out= 1’b1; end TWENTY: if(nickel_in) ns = TWENTY_FIVE; else if(dime_in) ns = THIRTY; dime_out= 1’b1; endcase
UCSD ECE 111, Prof. Koushanfar, Fall'17

20. UCSD ECE 111, Prof. Koushanfar, Fall'17
TWENTY_FIVE
case(ps) TWENTY_FIVE: if(nickel_in) ns = THIRTY; else if(dime_in) {ns, dispense} = {IDLE, 1’b1}; else if(quarter_in) begin // 25+25= {ns, dispense} = {IDLE, 1’b1}; nickel_out= 1’b1; dime_out= 1’b1; end endcase
UCSD ECE 111, Prof. Koushanfar, Fall'17

21. UCSD ECE 111, Prof. Koushanfar, Fall'17
THIRTY
case(ps) THIRTY: if(nickel_in) {ns, dispense} = {IDLE, 1’b1}; else if(dime_in) begin // 30+10=35+5 {ns, dispense} = {IDLE, 1’b1}; nickel_out= 1’b1; end else if(quarter_in) begin // 30+25= {ns, dispense} = {OWE_TEN, 1’b1}; // Go to OWE_TEN dime_out= 1’b1; end default: ns = IDLE; endcase
UCSD ECE 111, Prof. Koushanfar, Fall'17

22. OWE_TEN and Sequential
case(ps) OWE_TEN: begin dime_out= 1’b1; ns=IDLE; // immediately go back to IDLE end endcase clk) begin if(rst) begin ps <= IDLE; // reset end else begin ps <= ns;
(poseedge clk, posedge rst)
UCSD ECE 111, Prof. Koushanfar, Fall'17

23. UCSD ECE 111, Prof. Koushanfar, Fall'17
Example 2: Parking Lot
Consider a parking lot with a single entry and exit gate. Two pairs of photo sensors are used to monitor the activity of cars, as shown in the figure [Experiment in the book].
UCSD ECE 111, Prof. Koushanfar, Fall'17

24. UCSD ECE 111, Prof. Koushanfar, Fall'17
Parking Lot
When an object is between the photo transmitter and the photo receiver, the light is blocked and the corresponding output is asserted to 1. By monitoring the events of two sensors, we can determine whether a car is entering or exiting or a pedestrian is passing through.
UCSD ECE 111, Prof. Koushanfar, Fall'17

25. UCSD ECE 111, Prof. Koushanfar, Fall'17
Parking Lot
For example, the following sequence indicates that a car enters the lot:
Initially, both sensors are unblocked (i.e., the a and b signals are "00").
Sensor a is blocked (i.e., the a and b signals are " 10").
Both sensors are blocked (i.e., the a and b signals are "1 1 ").
Sensor a is unblocked (i.e., the a and b signals are "01 ").
Both sensors becomes unblocked (i.e., the a and b signals are "00").
UCSD ECE 111, Prof. Koushanfar, Fall'17

26. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM Diagram
Design an FSM with two input signals, a and b, and two output signals, enter and exit . The enter and exit signals assert one clock cycle when a car enters and one clock cycle when a car exits the lot, respectively. Derive the Verilog code for the FSM.
Parking Lot module a
enter
exit b
UCSD ECE 111, Prof. Koushanfar, Fall'17

27. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM
Lets’ draw a mealy FSM.
a b / exit entry
11/00
Idle
IN1
10/00
00/00
UCSD ECE 111, Prof. Koushanfar, Fall'17

28. UCSD ECE 111, Prof. Koushanfar, Fall'17
Entry
a b / exit entry
00/01
11/00
Idle
IN1
IN2
01/00
IN3
10/00
11/00
00/00
UCSD ECE 111, Prof. Koushanfar, Fall'17

29. UCSD ECE 111, Prof. Koushanfar, Fall'17
Exit
a b / exit entry
00/01
11/00
Idle
IN1
IN2
01/00
IN3
10/00
11/00
01/00
00/00
OUT1
11/00
OUT2
10/00
OUT3
00/10
UCSD ECE 111, Prof. Koushanfar, Fall'17

30. UCSD ECE 111, Prof. Koushanfar, Fall'17
Stay
00/01
a b / exit entry
11/00
10/00
11/00
01/00
Idle
IN1
IN2
IN3
10/00
11/00
01/00
01/00
00/00
OUT1
11/00
OUT2
10/00
OUT3
00/10
UCSD ECE 111, Prof. Koushanfar, Fall'17

31. UCSD ECE 111, Prof. Koushanfar, Fall'17
Otherwise
a b / exit entry
01/00
Idle
IN1
IN2
IN3
00/00
OUT1
OUT2
OUT3
UCSD ECE 111, Prof. Koushanfar, Fall'17

32. UCSD ECE 111, Prof. Koushanfar, Fall'17
Parking Lot Module
module parking_lot(
input wire clk, rst,
input wire a, b
output reg entry,
output reg exit );
endmodule
UCSD ECE 111, Prof. Koushanfar, Fall'17

33. UCSD ECE 111, Prof. Koushanfar, Fall'17
State Reg
module parking_lot(
input wire clk, rst,
input wire a, b
output reg entry,
output reg exit );
localparam IDLE=3’d0, IN1=3’d1, IN2=3’d2, IN3=3’d3, OUT1=3’d4, OUT2=3’d5, OUT3=3’d6;
reg [2:0] ps, ns; // 3-bit present state and next state
endmodule
UCSD ECE 111, Prof. Koushanfar, Fall'17

34. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM Template
begin // set all outputs to their inactive values. exit=0; entry=0; ns = IDLE; // by default we go to IDLE state. This simplifies the code. case(ps) default: ns = IDLE; endcase end
This is the Verilog template for FSM.
UCSD ECE 111, Prof. Koushanfar, Fall'17

35. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM: case(ps)
ns = ps; // by default we stay at the same state. case(ps) IDLE: if(a&~b) ns = IN1; else if(~a&b) ns = OUT1; IN1: else if(a&b) ns = IN2; IN2: if(a&b) ns = IN2; else if(~a&b) ns = IN3; endcase
UCSD ECE 111, Prof. Koushanfar, Fall'17

36. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM: case(ps)
case(ps) IN3: if(~a&b) ns = IN3; else if(~a&~b) {ns, entry} = {IDLE, 1’b1}; OUT1: if(~a&b) ns = OUT1; else if(a&b) ns = OUT2; OUT2: if(a&b) ns = OUT2; else if(a&~b) ns = OUT3; OUT3: if(a&~b) ns = OUT3; else if(~a&~b) {ns, exit} = {IDLE, 1’b1}; endcase
UCSD ECE 111, Prof. Koushanfar, Fall'17

37. UCSD ECE 111, Prof. Koushanfar, Fall'17
Sequential
clk) begin if(rst) begin ps <= IDLE; // reset end else begin ps <= ns; end
(poseedge clk, posedge rst)
UCSD ECE 111, Prof. Koushanfar, Fall'17

38. Example 3: Datapath and control
Digital systems perform sequences of
operations on encoded data
Datapath
Combinational circuits for operations
Registers for storing intermediate results
Control section: control sequencing
Generates control signals
Selecting operations to perform
Enabling registers at the right times
Uses status signals from datapath
UCSD ECE 111, Prof. Koushanfar, Fall'17

39. Example: Complex Multiplier
Cartesian form, fixed-point
operands: 4 integer, 12 fraction bits
result: 8 pre-, 24 post-binary-point bits
Subject to tight area constraints
4 multiplies, 1 add, 1 subtract
Perform sequentially using 1 multiplier, 1 adder/subtracter
UCSD ECE 111, Prof. Koushanfar, Fall'17

40. Complex Multiplier Datapath
UCSD ECE 111, Prof. Koushanfar, Fall'17

41. Complex Multiplier in Verilog
UCSD ECE 111, Prof. Koushanfar, Fall'17

42. Complex Multiplier in Verilog
UCSD ECE 111, Prof. Koushanfar, Fall'17

43. Multiplier Control Sequence
UCSD ECE 111, Prof. Koushanfar, Fall'17

44. Multiplier Control Sequence
UCSD ECE 111, Prof. Koushanfar, Fall'17

45. Multiplier Control Signals
UCSD ECE 111, Prof. Koushanfar, Fall'17

46. FSM: Multiplier Control
UCSD ECE 111, Prof. Koushanfar, Fall'17

47. UCSD ECE 111, Prof. Koushanfar, Fall'17
FSM in Verilog
UCSD ECE 111, Prof. Koushanfar, Fall'17

48. Multiplier Control in Verilog
UCSD ECE 111, Prof. Koushanfar, Fall'17