1. ISCA 2000 Panel
Slow Wires, Hot Chips, and Leaky Transistors: New Challenges in the New Millennium
Moderator: Shubu Mukherjee
VSSAD, Alpha Technology
Compaq Computer Corporation, Shrewsbury, Massachusetts
Technology drives architecture
This panel examines future technological challenges and potential research paths.
Such challenges include wire delay, power dissipation, and reliability problems.
Panelists: Bob Colwell, Dirk Grunwald, Norm Jouppi,
Mark Horowitz, Jim Smith, & T.N.Vijaykumar

2. Slow Wires For a circuit purist, “slow wire” is a blasphemy
a wire doesn’t get slower in absolute time when shrunk
a wire may get slower relative to a transistor when shrunk
Wire Delay Trends
Long wires don’t scale (RC delay constant)
+ short wires do scale with transistors!
Many “short wires” become “long wires” when shrunk
intrinsic RC of wire relatively higher than faster gates
New microarchitectures typically increase wire lengths
accessing global resources cause problem
transition to next slide: new architectures increase wire length .. they also increase power dissipation

3. Hot Chips & Leaky Transistors
Dynamic Power Explosion
100 Watts in 1999 to 2000 Watts in 2010, Borkar, IEEE Computer, July/Aug, 1999.
Static Power from Leaky Transistors
10% of dynamic power in 0.1 micron technology, Thompson, et al. Intel Technology Journal, Q3, 1998.
Peak vs. average power dissipation
peak power important for packaging cost
average power important for battery life
Hot chips have reliability problems … transition to next slide

4. Fault Tolerance Transistors are less reliable Future is worse
permanent faults
transient faults (> 80%)
Future is worse
smaller feature size
lower voltage
higher transistor count
reduced noise margin
Fault detection & recovery
examples of permanent and transient faults
cosmic rays … which leads to “Future is worse”

5. Abstract, Model, & Solve
New technologies enable new architectural designs
GREAT news for architects!
Abstraction: understand the problem
e.g., long wires are problematic, not short wires
Tools to model the problem
e.g., wire delays, power models, fault coverage?
Solutions to the problem
explore performance/technology tradeoffs

6. Panelists Prof. Mark Horowitz, Stanford University
Prof. T.N.Vijaykumar, Purdue University
Prof. Dirk Grunwald, U. of Colorado, Boulder
Dr. Norm Jouppi, WRL, Compaq
Prof. Jim Smith, U. of Wisconsin-Madison
Dr. Bob Colwell, Intel
Bob: user-friendly and fault-tolerant
Dirk: microarchitectural tricks for power
Mark: reachability is problem, avoid global resources, make things simpler
Norm: chip-multiprocessors will tackle slow wires and hot chips
Jim Smith: distributed architectures with dependent instructions scheduled together
Vijay: static power dissipation