1. Sungho Kang Yonsei University
Boundary Scan
Sungho Kang
Yonsei University

2. Outiline Introduction TAP Controller Instruction Register
Test Data Registers
Instructions
Hardware Test Innovations
PCB Test
Conclusion

3. Boundary Scan
Introduction
Improve testability by reducing the requirements placed on the physical test equipment
Also called
JTAG (Joint Test Action Group) Boundary Scan Standards
IEEE P1149.1
Why use it?
Testing interconnections among chips
Testing each chip
Snapshot observation of normal system data
Why testing boards?
To test board is easier than to test systems
Board Test Philosophy
As a sorting process
As a repair driver
As a process monitor

4. Boundary Scan Chip Architecture
Introduction
The scan paths are connected via the test bus circuitry
Connection from TDI to Sin
Connection from TDO to Sout
The normal I/O terminals of the application logic are connected through boundary scan cells to the chips I/O pads
Operation
An instruction is sent serially over the TDI line into the instruction register
The selected test circuitry is configured to respond to the instruction
The test instruction is executed and then test results can be shifted out of selected registers and transmitted over the TDO to the bus master
Possible to shift new data into registers using the TDI while results are shifted out and transmitted over the TDO line

5. Boundary Scan Chip Architecture
Introduction

6. Board Test Board containing 4 chips with one serial test path
Introduction
Board containing 4 chips with one serial test path

7. Cost of Boundary Scan Costs Impacts
Introduction
Costs
4 or 5 pins - Test Access Port (TAP)
16 state machine - TAP controller
Boundary scan register
Bypass register - one stage
Instruction register - 2 or more stages
Impacts
Enhanced diagnosis
Reduced test-repair looping
Standardized tests
Reuse of tests
Reduced access problems

8. Test Access Port
TAP
Consisting of the ports associated with TMS, TCK, TDI and TDO
TCK: Test Clock
Operate BS part of the ICs synchronously and independently of the built-in system clock
TDI : Test Data In
Data is shifted in at the rising edge
TDO: Test Data Out
Data is shifted out at the falling edge
TMS: Test Mode Select
TMS signals are sampled at the rising edge
Controls transitions of controller
TRST : Test Reset (Optional)
TAP's test logic is asynchronously forced into its reset mode when a logic 0 is applied to TRST

9. Test Bus
TAP
Each chip is considered to be a bus slave and the bus is assumed to be driven a bus master
Ring Connection
One TMS
Star Connection
Each chip is associated with its own TMS signal
Hybrid Connection
Combined

10. Ring and Star Test Bus
TAP

11. Functions of TAP Controller
Generate clock and control signals required for the correct sequence of operations
Provide signals to allow loading the instructions into the Instruction Register
Provide signals to shift test data into (TDI) and test result data out of (TDO) the shift registers
Perform test actions such as capture, shift and test data

12. TAP Controller State Diagram
Non-shaded states : auxiliary
Do not initiate a system action but are included to provide process control

13. Instruction Register Allows instruction to be shifted into chip
Can be used to specify operations to be executed and select test data registers
Each instruction enables a single serial test data register path between TDI and TDO
Instruction may vary per IC on the board
Serial-in parallel-out register

14. Instruction Register
Instruction Register
IR must contain at least 2 shift-register-based cells which can hold instruction data
These 2 mandatory cells are located nearest to the serial outputs, i.e. they are the least significant bits
Used in locating faults through the IC's
Set up

15. Test Data Registers Required Optional Unique Name Fixed Length
Boundary Scan Register
Bypass Register
Optional
Device Identification Register : specifies manufacturer, part number, and variant
Design Specific Register : for self test, internal scan paths, etc.
Unique Name
Fixed Length

16. Bypass Register Single stage shift register
When selected, the shift register is set to 0 on the rising edge of TCK with
TAP controller in its Capture-DR state
Provide a minimum length serial path for the test data from TDI to TDO
Test cycle is shortened
Diagnosis time is shortened

17. Boundary Scan Register
Scan Cell
Series of boundary scan cells
Features
Allow testing of circuitry external to the IC
Allow testing of the core logic
Allow sampling and examination of the input and output signals without interfering the operation of the core logic
Can stay idle

18. Boundary Scan Cells Implementation of boundary scan cell Normal Mode
When Mode Test/Normal = 0, data passes from IN to OUT
Then the cell is transparent to the application logic
Scan Mode
Mode Shift/Load =1 and clock pulses are applied to Clock
Capture Mode
The data on IN can be loaded into the scan path by setting Mode Shift/Load =0 and applying one clock pulse to Clock

19. Boundary Scan Cells Update Mode
Once the 1st FF is loaded, either by a capture or scan operation, its value can be applied to OUT by setting Mode Test/Normal=1 and applying clock pulse to Update
Minimum boundary scan cell configuration for input pins
Preferrable in delay sensitive circuits

20. Instructions Mandatory Optional BYPASS SAMPLE/PRELOAD EXTEST INTEST
RUNBIST
IDCODE
USERCODE
CLAMP
HIGHZ
Design specific

21. BYPASS
Instructions
Every chip must have a BYPASS register which is a test data register of length 1
Provides a single bit connection through the chip
data shifted through chip without affecting chip
shorten path to target chip
Binary code must be all 1's
If the optional device ID is not present, BYPASS instruction is forced into the latches at the parallel outputs of the Instruction Register when the TAP controller is in its Test-Logic-Reset

22. SAMPLE/PRELOAD
Instructions
Used to take snapshot of normal system operation stage into the parallel instruction register
Allows the data on I/O pads of a chip to be sampled
Useful for debugging of prototypes in the development phase of a board design
Used to load values into boundary Scan cells
After power-up, the data in boundary scan registers at the output cells are not known

23. EXTEST
Instructions
Used to test circuitry external to a chip, such as the board interconnect
While this instruction is executed, the core logic is isolated from the I/O pins
The test data is loaded beforehand into the boundary scan register stages using SAMPLE/PRELOAD
The loading of test vectors is concluded by bridging the TAP controller to the Update-DR state
On the falling edge of TCK the test vectors are transferred to the parallel output stage
At the receiving ends of the net, the cells at the input pins capture the test result with the controller in its Capture-DR state
The next step shifts out the test results from the input pin cells towards TDO

24. EXTEST Dataflow during EXTEST instruction
Instructions
Dataflow during EXTEST instruction
During the time of execution of the EXTEST, only one system pin is driving a net at a time while the other connected output pins are kept at HIGHZ
This avoids boundary scan cells at the output pins being overdriven with an unknown signal value

25. INTEST
Instructions
Used to apply a test vector to the application logic via the boundary scan path and to capture the response from this logic
Slow speed testing
Gives complete controllability and observability of the I/O pads of a chip
For device containing dynamic logic such as DRAM memories, refreshment of data cells may require a much higher frequency than can be obtained with this test method
Use RUNBIST

26. INTEST
Instructions
Dataflow during INTEST instruction

27. RUNBIST Allows for the execution of a self test process
Instructions
Allows for the execution of a self test process
The test is executed while TAP controller is in the Run-Test/Idle state
Must select the boundary scan register to be connected between TDI and TDO
All inputs to the application logic are driven by the boundary scan register during the execution of this instruction
The timing constraints have been added to ensure that the tests of all components involved are completed in one test run
When the self test is running, the boundary scan cells are used to hold the component's output to a fixed value
The signals generated in the core logic during the self test cannot enter the PCB nets
When RUNBIST is applied, the test results of all versions of a component must be the same

28. CLAMP
Instructions
Used to control the output signals of a component to a constant level by means of a boundary scan cell
In such cases the Bypass Register is connected in the TDI-TDO path on the PCB
This instruction is used for instance with cluster testing, where it can be necessary to apply static guarding values to those pins of a logic circuitry which are not involved in a test
The required signal values are loaded together with all test vectors, both at the start of the test and each time a new test pattern is loaded
Increase the test pattern and slightly reduce the overall test rate

29. IDCODE
Instructions
If a Device Identification Register is included, the IDCODE is forced into the Instruction Register's parallel output latches while the TAP controller is in its Test-Logic-Reset state
This means of accesses to the Device Identification Register permits blind interrogation of components assembled onto a PCB, making it possible to determine what components are mounted on a board

30. USERCODE
Instructions
Must provided by the manufacturer if the Device Identification Register is included in a component and the component is user-programmable
This instruction is only required if the programming can not be determined through the use of the test logic
When selected, this instruction loads the user-programmable identification code into the Device Identification Register at a rising edge of TCK and TAP controller in its Capture-DR state

31. HIGHZ Force all outputs of a component to an inactive drive state
Instructions
Force all outputs of a component to an inactive drive state
Application is found in situations where a conventional in-circuit test is still required
The in-circuit tester may drive signals back to the component's output pins where hazards may occur if its output impedance is not high

32. Binary Counting Test Sequence
PCB Test-Algorithm
Only two vectors are needed to detect any short
Vectors for short detection
V1 V2
Net
Net
Net
Net
The vectors V can be applied in parallel
Test time is determined by log2(n)
If the test vectors are applied through a boundary scan, test time is p log2(n) where p is the number of shift operations
If the all-0 and all-1 test patterns are avoided for the short test the same test vectors can be used to detect both short and stuck-at faults
log2(n+2) vectors are necessary and sufficient to to test a set of n nets on both type of faults

33. Binary Counting Test Sequence
PCB Test-Algorithm
Algorithm
Step1 : Assign each of the n interconnect nets a successive number, starting with 1
Step2 : Calculate the value of log2(n+2) in order to find the number of patterns needed
Step3 : Assign each of driving node the calculated number of bits with a bit pattern having a binary value equal to the number assigned to the net concerned
Vectors for short detection of 6 connections
V1 V2 V3
Net
Net
Net
Net
Net
Net

34. Walking One Sequence
PCB Test-Algorithm
If there are N nets, then after N shifts of the total chain the logical 1 has walked over the all nets, one at a time … …
The total sequence just takes N vectors
It guarantees full diagnosis
It works well for single fault situations and for independent co-existing of the same type
Test patterns are easy to generate and test result is easily measured by a simple counter
It is suited for go/no-go test but the application time is long
Netlist information is needed
A walking zero sequence can also be used

35. Maximal Independent Set
PCB Test-Algorithm
Potential weight
depends on the bit positions of the highest and lowest bit with a value 1 in a STV
For a non-zero vector v=(b0,b1…bn….bm) where bn=bm=1, the potential weight w is given by w=m-n+1
The vector set exhibits a very regular pattern
The subsets with equal potential weight are diagonally independent

36. Aliasing Test Results
PCB Test - Diagnositcs
An aliasing test results exists when the faulty response of a set of shorted nets is the same as the fault-free response of another net
In this case it cannot be determined whether or not the fault-free net is involved in the short

37. Confouding Test Results
PCB Test - Diagnositcs
It may happen that 2 or more independent shorts occur in a set of nets on a PCB
A confounding test result may occur when the test results from the multiple independent faults are identical
It cannot be determined if these faults are independent
The degree of a confounding test result is defined as the maximum number of potentially independent faults that all have the same test result
A full diagnosis after a one-step test procedure is only possible if neither a confounding nor an aliasing test result exists

38. Cluster Testing
PCB Test-Cluster Testing
Circuit containing boundary scan logic and non-boundary scan login
A cluster may have its inputs and outputs connected to boundary scan ICs to other circuitry or to board connectors
The test stimulus for the cluster is loaded through the TDI-TDO path into the relevant BS output cells and the responses are captured in boundary input cells and shifted out for diagnosis
Clusters may be subdivided into various types of cluster
Memory array of clusters
Single device clusters
Random logic clusters
Tester must know the PCB topology in order to select the meaningful test data out of the entire background data stream