1. CS-3013 Operating Systems Hugh C. Lauer
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CS-3013 Operating Systems Hugh C. Lauer
(Slides include materials from Slides include materials from Modern Operating Systems, 3rd ed., by Andrew Tanenbaum and from Operating System Concepts, 7th ed., by Silbershatz, Galvin, & Gagne)
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2. Review – Memory Management
Allocation of physical memory to processes
Virtual Address
Address space in which the process “thinks”
Each virtual address is translated “on the fly” to a physical address
Fragmentation
Internal fragmentation – unused within an allocation
External fragmentation – unused between allocations
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3. Review – Memory Management (cont’d)
Segmentation
Recognition of different parts of virtual address space
Different allocation strategies
The rule of “no free lunch”
Fixed size allocations  no external fragmentation, more internal fragmentation
Variable allocations  no internal fragmentation, more external fragmentation
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4. Reading Assignment Tanenbaum
§§ (previous topic – Memory Management)
§ 3.3 (this topic on Paging)
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5. Paging A different approach
Addresses all of the issues of previous topic
Introduces new issues of its own
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6. Memory Management Processor MMU Memory I/O Devices Logical Addresses
Virtual (or logical) address vs. Physical address
Memory Management Unit (MMU)
Set of registers and mechanisms to translate virtual addresses to physical addresses
Processes (and processors) see virtual addresses
Virtual address space is same for all processes, usually 0 based
Virtual address spaces are protected from other processes
MMU and devices see physical addresses
Processor
MMU
Memory
I/O Devices
Logical Addresses
Physical Addresses
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7. Logical Address Space (virtual memory)
Paging
Use small fixed size units in both physical and virtual memory
Provide sufficient MMU hardware to allow page units to be scattered across memory
Make it possible to leave infrequently used parts of virtual address space out of physical memory
Solve internal & external fragmentation problems
page X
frame 0
frame 1
frame 2
frame Y
physical memory …
page 0
page 1
page 2
Logical Address Space (virtual memory)
page 3
MMU
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8. Paging Processes see a large virtual address space
Either contiguous or segmented
Memory Manager divides the virtual address space into equal sized pieces called pages
Some systems support more than one page size
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9. Paging (continued)
Memory Manager divides the physical address space into equal sized pieces called frames
Size usually a power of 2 between 512 and 8192 bytes
Some modern systems support 64 megabyte pages!
Frame table
One entry per frame of physical memory; each entry is either
Free
Allocated to one or more processes
sizeof(page) = sizeof(frame)
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10. Address Translation for Paging
Translating virtual addresses
a virtual address has two parts: virtual page number & offset
virtual page number (VPN) is index into a page table
page table entry contains page frame number (PFN)
physical address is: startof(PFN) + offset
Page tables
Supported by MMU hardware
Managed by the Memory Manager
Map virtual page numbers to page frame numbers
one page table entry (PTE) per page in virtual address space
i.e., one PTE per VPN
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11. Paging Translation … page frame 0 frame 1 frame 2 frame Y frame 3
physical memory
offset
physical address
F(PFN)
page frame #
page table
virtual address
virtual page #
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12. Page Translation Example
Assume a 32-bit contiguous address space
Assume page size 4KBytes (log2(4096) = 12 bits)
For a process to address the full logical address space
Need 220 PTEs – VPN is 20 bits
Offset is 12 bits
Translation of virtual address 0x
Offset is 0x678
Assume PTE(0x12345) contains 0x01010
Physical address is 0x
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13. Generic PTE Structure
page frame number
prot M R V 20 2 1
Valid bit gives state of this Page Table Entry (PTE)
says whether or not its virtual address is valid – in memory and VA range
If not set, page might not be in memory or may not even exist!
Reference bit says whether the page has been accessed
it is set by hardware whenever a page has been read or written to
Modify bit says whether or not the page is dirty
it is set by hardware during every write to the page
Protection bits control which operations are allowed
read, write, execute, etc.
Page frame number (PFN) determines the physical page
physical page start address
Other bits dependent upon machine architecture
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14. Paging – Advantages Easy to allocate physical memory
pick (almost) any free frame
No external fragmentation
All frames are equal
Minimal internal fragmentation
Bounded by page/frame size
Easy to swap out pages (called pageout)
Size is usually a multiple of disk blocks
PTEs may contain info that help reduce disk traffic
Processes can run with not all pages swapped in
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15. Definition — Page Fault
Trap when process attempts to reference a virtual address in a page with Valid bit in PTE set to false
E.g., page not in physical memory
If page exists on disk:–
Suspend process
If necessary, throw out some other page (& update its PTE)
Swap in desired page, resume execution
If page does not exist on disk:–
Return program error or
Conjure up a new page and resume execution
E.g., for growing the stack!
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16. Steps in Handling a Page Fault
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17. Definition — Backing Storage
A place on external storage medium where copies of virtual pages are kept
Usually a hard disk (locally or on a server)
Place from which contents of pages are read after page faults
Place where contents of pages are written if page frames need to be re-allocated
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18. Backing Storage Executable code and constants:–
The loadable image file produced by compiler
Working memory (stack, heap, static data)
Special swapping file (or partition) on disk
Persistent application data
Application data files on local or server disks
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19. Requirement for Paging to Work!
Machine instructions must be capable of restarting
If execution was interrupted during a partially completed instruction, need to be able to
continue or
redo without harm
This is a property of all modern CPUs …
… but not of some older CPUs!
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20. Protection Bits Protection bits are important part of paging
A process may have valid pages that are
not writable
execute only
etc.
E.g., setting PTE protection bits to prohibit certain actions is a legitimate way of detecting the first action to that page.
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21. Protection Bits (continued)
Definition of Page Fault is extended to include:–
Trap when process attempts to reference a virtual address in a page with Valid bit in PTE set to false OR
Access inconsistent with protection setting
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22. Example
A page may be logically writable, as required by the application, but …
… setting PTE bits to disallow writing is a way of detecting the first attempt to write
Take some action
Reset PTE bit
Allow process to continue as if nothing happened
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23. Questions?
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24. Observations and Definitions
Recurring themes in paging
Temporal Locality – locations referenced recently tend to be referenced again soon
Spatial Locality – locations near recent references tend to be referenced soon
Definitions
Working set: The set of pages that a process needs to run without frequent page faults
Thrashing: Excessive page faulting due to insufficient frames to support working set
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25. Paging Issues #1 — Page Tables can consume large amounts of space
If PTE is 4 bytes, and use 4KB pages, and have 32 bit VA space  4MB for each process’s page table
Stored in main memory!
What happens for 64-bit logical address spaces?
#2 — Performance Impact
Converting virtual to physical address requires multiple operations to access memory
Read Page Table Entry from memory!
Get page frame number
Construct physical address
Assorted protection and valid checks
Without fast hardware support, requires multiple memory accesses and a lot of work per logical address
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26. Issue #1: Page Table Size
Process Virtual Address spaces
Not usually full – don’t need every PTE
Processes do exhibit locality – only need a subset of the PTEs
Two-level page tables
I.e., Virtual Addresses have 3 parts
Master page number – points to secondary page table
Secondary page number – points to PTE containing page frame #
Offset
Physical Address = offset + startof (PFN)
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27. Two-level page tables … 12 bits 8 bits 12 bits page frame 0 frame 1
frame Y …
frame 3
physical memory
offset
physical address
page frame #
master
page table
secondary page#
virtual address
master page #
secondary
page table #
page table # addr
page frame
number
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28. Note Note: Master page number can function as Segment number
previous topic
n-level page tables are possible, but rare in 32-bit systems
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29. Core i7 Page Translation
CR3
Physical
address
of page
of L1 PT 9
VPO 12
Virtual
L4 PT
Page
table
L4 PTE
PPN
PPO 40
Offset into
physical and
virtual page
VPN 3
VPN 4
VPN 2
VPN 1
L3 PT
Page middle
directory
L3 PTE
L2 PT
Page upper
L2 PTE
L1 PT
Page global
L1 PTE /
512 GB
region
per entry
1 GB
2 MB
4 KB
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30. Multilevel Page Tables
Sparse Virtual Address space – very few secondary PTs ever needed
Process Locality – only a few secondary PTs needed at one time
Can page out secondary PTs that are not needed now
Don’t page Master Page Table
Save physical memory
However
Performance is worse
Now have 3 (or more) memory accesses per virtual memory reference or instruction fetch
How do we get back to about 1 memory access per VA reference?
Problem #2 of “Paging Issues” slide
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31. Paging Issues #1 — Page Tables can consume large amounts of space
If PTE is 4 bytes, and use 4KB pages, and have 32 bit VA space  4MB for each process’s page table
Stored in main memory!
What happens for 64-bit logical address spaces?
#2 — Performance Impact
Converting virtual to physical address requires multiple operations to access memory
Read Page Table Entry from memory!
Get page frame number
Construct physical address
Assorted protection and valid checks
Without fast hardware support, requires multiple memory accesses and a lot of work per logical address
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32. Solution — Associative Memory aka Dynamic Address Translation — DAT aka Translation Lookaside Buffer — TLB
VPN #
PTE
Do fast hardware search of all entries in parallel for VPN
If present, use page frame number from PTE directly
If not,
Look up in page table (multiple accesses)
Load VPN and PTE into Associative Memory (throwing out another entry as needed)
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33. Translation Lookaside Buffer (TLB)
Associative memory implementation in hardware
Translates VPN to PTE (containing PFN)
Done in single machine cycle
TLB is hardware assist
Fully or partially associative – entries searched in parallel with VPN as index
Returns page frame number (PFN)
MMU use PFN and offset to get Physical Address
Locality makes TLBs work
Usually have 8–1024 TLB entries
Sufficient to deliver 99%+ hit rate (in most cases)
Works especially well with multi-level page tables
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34. MMU with TLB
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35. Typical Machine Architecture
CPU
Bridge
Memory
Graphics
I/O device
MMU and TLB live here
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36. TLB-related Policies
OS must ensure that TLB and page tables are consistent
When OS changes bits (e.g. protection) in PTE, it must invalidate TLB copy
Dirty bit and reference bits in TLB must be written back to PTE
TLB replacement policies
Random
Least Recently Used (LRU) – with hardware help
What happens on context switch?
Each process has own page tables (possibly multi-level)
Must invalidate all TLB entries
Then TLB fills up again as new process executes
Expensive context switches just got more expensive!
Note benefit of Threads sharing same address space
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37. Questions?
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38. Alternative Page Table format – Hashed
Common in address spaces > 32 bits.
The virtual page number is hashed into a page table.
Each entry contains a chain of VPN’s with same hash.
Search chain for match
If found, use associated PTE
Still needs TLB for performance
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39. Hashed Page Tables
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40. Alternative Page Table format – Inverted
One entry for each real page of memory.
Entry consists of virtual address of page stored at that real memory location, with information about the process that owns that page.
Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.
Use hash table to limit the search to one or a few page-table entries.
Still uses TLB to speed up execution
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41. Inverted Page Table Architecture
See also Tanenbaum, Fig 3-14
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42. Inverted Page Table Architecture (continued)
Apollo Domain systems
Common in 64-bit address systems
Supported by TLB
Next topic helps to quantify size of TLB
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43. Paging – Some Tricks
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44. Paging – Some Tricks Shared Memory Copy on Write
Mapping Files to Virtual Memory
Guard pages, segments, and Virtual Memory Organization
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45. Shared Memory
Part of virtual memory of two or more processes map to same frames
Finer grained sharing than segments
Data sharing with Read/Write
Shared libraries with eXecute
Each process has own PTEs – different privileges
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46. Shared Pages (illustration)
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47. Shared Pages (continued)
Widely used for libraries of code
Supported by most modern operating systems
Less widely used for sharing data memory
shmget(), etc.
Not always as same virtual address in each virtual memory — causes complications
Old gimmick serving same purpose as threads today
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48. Questions?
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49. Paging trick – Copy-on-write
During fork()
Don’t copy individual pages of virtual memory
Just copy page tables; all pages start out shared
Set all PTEs to read-only in both processes
When either process hits a write-protection fault on a valid page that should be writable
Make a copy of that page, set write protect bit in PTE to allow writing
Resume faulting process
Saves a lot of unnecessary copying
Especially if child process will delete and reload all of virtual memory with call to exec()
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50. Definition — Mapping Mapping (part of) virtual memory to a file
 Assigning blocks of file as backing store for the virtual memory pages, so that
Page faults in (that part of) virtual memory resolve to the blocks of the file
Dirty pages in (that part of) virtual memory are written back to the blocks of the file
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51. Warning — Memory-mapped Files
Tempting idea:–
Instead of standard I/O calls (read(), write(), etc.) map file starting at virtual address X
Access to “X + n” refers to file at offset n
Use paging mechanism to read file blocks into physical memory on demand …
… and write them out as needed
Has been tried many times
Rarely works well in practice
Hard to program; even harder to manage performance
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52. Paging – Some Tricks Shared Memory Copy on Write
Mapping Files to Virtual Memory
Guard pages, segments, and Virtual Memory Organization
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53. Virtual Memory Organization
From an earlier topic
Virtual Memory Organization 0x
0xFFFFFFFF
Virtual
address space
program code
(text)
static data
heap
(dynamically allocated)
stack PC SP
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54. Virtual Memory Organization
From an earlier topic
Virtual Memory Organization
program code
(text)
static data
heap
(dynamically allocated)
stack PC SP
Map to writable swap file
Unmapped, may be dynamically mapped
guard page (never mapped)
Map to writable swap file
Map to writable swap file
Mapped to read-only executable file
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55. Virtual Memory Organization (continued)
thread 3 stack
program code
& constants
static data
heap
thread 1 stack
PC (T2)
SP (T2)
thread 2 stack
SP (T1)
SP (T3)
PC (T3)
guard page (never mapped)
guard page
Mapped to read-only executable file
Map to writable swap file
Unmapped, may be dynamically mapped
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56. Virtual Memory Organization (continued)
Each area of process VM is its own segment (or sequence of segments)
Executable code & constants – fixed size
Shared libraries
Static data – fixed size
Heap – open-ended
Stacks – each open-ended
Other segments as needed
E.g., symbol tables, loader information, etc.
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57. Summary
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58. Virtual Memory – a Major OS Abstraction
Processes execute in virtual memory, not physical memory
Virtual memory may be very large
Much larger than physical memory
Virtual memory may be organized in interesting & useful ways
Open-ended segments
Virtual memory is where the action is!
Physical memory is just a cache of virtual memory
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59. Reading Assignment Tanenbaum
§§ (previous topic – Memory Management)
§ 3.3 (this topic on Paging)
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60. Related topic – Caching
Questions?
Related topic – Caching
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