1. Another Physical Layer – I2C
Multi-mastered
Send and receive
Two wire (plus ground)
Serial
CSE 466 – Fall Introduction - 1

2. CSE 466 – Fall 2000 - Introduction - 2
Terminology
CSE 466 – Fall Introduction - 2

3. CSE 466 – Fall 2000 - Introduction - 3
Physical Interface
wired-and configuration
CSE 466 – Fall Introduction - 3

4. CSE 466 – Fall 2000 - Introduction - 4
Bit Transfer
Transmitter
(master or slave)
sampled on both edges
Master
CSE 466 – Fall Introduction - 4

5. CSE 466 – Fall 2000 - Introduction - 5
Who gets to be master
The one who initiates a frame:
A frame is:
<Start><addr><data>…<data><Stop> OR
<Start><addr><data>…<data><R_Start><addr><data>…<Stop>
CSE 466 – Fall Introduction - 5

6. CSE 466 – Fall 2000 - Introduction - 6
An I2C Byte Transfer
MSB First
MSB……………….LSB
slave
slave
Tx Device
Rx Device
master
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7. CSE 466 – Fall 2000 - Introduction - 7
A Complete Frame
MSB……..LSB
Addresses are 7 bits, LSB of address byte is Read/Write control.
Determines whether master or slave becomes the transmitter
CSE 466 – Fall Introduction - 7

8. CSE 466 – Fall 2000 - Introduction - 8
Arbitration
It is up to the failed master to try again when the bus is not busy.
Seems like high address devices are low priority receivers…but I haven’t read this anywhere
CSE 466 – Fall Introduction - 8

9. CSE 466 – Fall 2000 - Introduction - 9
Interfacing to the Bus
8051
Electrical connection is fine. But the software is complex
CSE 466 – Fall Introduction - 9

10. CSE 466 – Fall 2000 - Introduction - 10
An alternative
8051
addr (1bit) A0
PCF
8584
I2C
Bus
Controller
data (8 bits) P0 DB
rst
CK2
\CS
\RD
\WR
Memory mapped device that handles bit level interface.
Only do byte level stuff in software
CSE 466 – Fall Introduction - 10

11. Using the Bus Interface
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12. CSE 466 – Fall 2000 - Introduction - 12
Slave Flow
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13. CSE 466 – Fall 2000 - Introduction - 13
Slave Receiver Mode
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