1. Jason Gilmore Vadim Khotilovich Alexei Safonov Indara Suarez
TMB Mezzanine Upgrade
Jason Gilmore
Vadim Khotilovich
Alexei Safonov
Indara Suarez
Muon Electronics Upgrade Workshop
The Ohio State University
April 23-24, 2010

2. Mezz Design Considerations - I
Virtex 6 FPGA enhances our capabilities
5-fold increase in logic, double the speed
Required for improved trigger algorithms
…it also adds some complications
Requires 6 voltage levels, ~10 amps total
Can CRB deliver this current?
Necessitates 7 linear regulators
Makes extra heat, can the racks handle this?
Virtex 6 I/O is limited to 2.5V
Current TMB uses 3.3V signals throughout
Require external voltage translators for Virtex 6

3. Snap 12 Fiber
Receiver
Virtex 6 FPGA + PROM
Level-shifting translators
QPLL
Snap 12 Fiber
Transmitter
Voltage Regulators

4. Mezz Design Considerations - II
Maintain full functionality for all CFEB contingencies
Requires new board to be backwards compatible
Keep the copper connections for old CFEBs
Make fiber inputs available for new dCFEBs
Allows simple upgrade installation
Replace old TMB mezzanines with the new one
Plugs into socket on TMB, four screws secure it
Replace TMB front panels
New panel will allow for dCFEB fiber connector
Does not require a long shutdown
Could be installed one crate at a time, ~2 per day
When dCFEBs are installed, just plug in fibers and update the TMB firmware

5. Board Design Plans, ~Now
We have built a voltage regulator test board
Try a variety of regulators from different manufacturers
Used to test cooling ideas, effectiveness
Will use this board for regulator radiation tests
Work done with a grad student (Indara Suzarez)
REU student to join in the summer

6. Board Design Plans, Soon
Working on new mezzanine prototype
Schematic and layout work in progress
Expecting a board available this summer
SNAP 12 fiber components on order
All other parts (FPGAs, etc) are in hand
Use Xilinx XC6VLX195T-2FFG1156CES
Backward compatibility tests
Current firmware being ported to Virtex-6 by UCLA
Plan to follow up with several more boards (e.g. for use at UCLA, Rice)

8. Board Design Plans, Further
Moving forward
Tests with the new prototypes
Optical link tests, VME testing, etc.
Prototype will have both optical receiver and transmitter for maximum testing flexibility
New firmware:
Working (with Vadim) on documentation for new algorithms to be implemented in new firmware code
Collaborate closely with UCLA on actual implementation of firmware

9. Summary
Focusing on a design that minimizes effect of schedule contingencies or constraints:
Fully compatible with old and future CFEBs
Possible installation without a shutdown?
TMB mezzanine effort in progress:
A prototype is coming this summer
Investigating potential concerns
Power, cooling, also will need to look at radiation hardness
A real test will be putting a new TMB into the crate and making it work