Presentation is loading. Please wait.

Presentation is loading. Please wait.

SYEN 3330 Digital Systems Chapter 7 – Part 1 SYEN 3330 Digital Systems.

Similar presentations


Presentation on theme: "SYEN 3330 Digital Systems Chapter 7 – Part 1 SYEN 3330 Digital Systems."— Presentation transcript:

1 SYEN Digital Systems Chapter 7 – Part 1 SYEN 3330 Digital Systems

2 Registers SYEN 3330 Digital Systems

3 Example: 2-bit Register
SYEN 3330 Digital Systems

4 Registers: Storage Model
SYEN 3330 Digital Systems

5 Registers with Clock Gating
Load signal is used to enable the clock signal to pass through if 1 and prevent the clock signal from passing through if 0. Example: For Positive Edge Triggering or Neg. Pulse MS What logic is needed for gating? What is the problem? Master Clock Load Gated Clock to FF Clock Skew of GC SYEN 3330 Digital Systems

6 Registers with Load Control
SYEN 3330 Digital Systems

7 Registers with Load Control
SYEN 3330 Digital Systems

8 Shift Registers SYEN 3330 Digital Systems

9 Shift Registers (Continued)
SYEN 3330 Digital Systems

10 Parallel Load Shift Registers
SYEN 3330 Digital Systems

11 Shift Registers with More Functions
SYEN 3330 Digital Systems

12 Serial Data Operations
SYEN 3330 Digital Systems

13 Serial Adder SYEN 3330 Digital Systems


Download ppt "SYEN 3330 Digital Systems Chapter 7 – Part 1 SYEN 3330 Digital Systems."

Similar presentations


Ads by Google