1. 4541.633A SoC Design Automation Seoul National University
Hardware Modeling
A SoC Design Automation
School of EECS
Seoul National University

2. Abstraction Levels and Synthesis Flow
Introduction
Introduction
Abstraction Levels and Synthesis Flow
language models
abstract models * + -
< v1 v2 v6 v3 v4 v7 v8
v10
v11 v9 v5 3 x u dx y a xl ul yl c
compilation
operations & dependencies
(control/data-flow graph)
HDL
behavioral view
module DIFFEQ (x, y, u, dx, a, clock, start);
inout [7:0] x, y, u;
input [7:0] a, dx;
input clock, start;
reg [7:0] xl, ul, yl;
always
wait (start);
begin
while (x < a)
xl = x +dx;
yl = y + (u*dx);
ul = u - (3*x*u*dx) - (3*y*dx);
@(posedge clock);
x = xl; u = ul; y = yl;
end
endmodule
architectural
synthesis/optimization
control
compilation
FSMs and logic functions
(state tables & logic networks)
HDL * *
+, -, < +
structural view
logic
synthesis/optimization
translation R
D Q
interconnected logic blocks
(logic networks)
HDL

3. Architectural Synthesis
Introduction
Y-Chart
Structural
Behavioral
System Synthesis
Processor, Memory, Switch
Algorithm (D.S.)
Architectural Synthesis
ALU, MUX, Register, Control
Control/Data Flow (Word)
Logic Synthesis
Gates
FSM, Boolean Equation (Logic)
Transistors
Circuit (Transfer Function)
Cell Layout
Module Floor Plan
Processor Floor Plan
System Floor Plan
Physical

4. Hardware Description Languages
Hardware (vs. software)
Concurrency (parallel computer)
Structural information as well as behavioral information
Timing (real time software)
HDL
syntax, semantics, pragmatics
Procedural: sequence is important, VHDL (behavioral), C
Declarative: order of statements is not important, VHDL(structural, data-flow), CIF, LISP
Imperative: assignment (statement oriented), VHDL(behavioral), C
Applicative: function invocation (functional), Silage, LISP
Mostly procedural and imperative
Physical: CIF, GDSII
Structural: EDIF
Behavioral:
VHDL

5. Hardware Description Languages
Example (Euler’s method for solving differential equation)
y’’ + 3xy’ + 3y = 0
initial value: x=x0, y(x0), y’(x0)
y(a) = ?
stepsize = dx
xi+1 = xi + dx
u = y’
u’ + 3xu + 3y = 0
ui+1 = ui + ui’dx = ui - 3xiuidx - 3yidx
yi+1 = yi +yi’dx = yi+uidx
VHDL
package mypack is
subtype bit8 is integer range 0 to 255;
end mypack;
use work.mypack.all
entity DIFFEQ is
port( dx_port, a_port, x_port, u_port : in bit8;
y_port : inout bit8;
clock, start : in bit);
end DIFFEQ;

6. Hardware Description Languages
architecture BEHAVIOR of DIFFEQ is
begin
process
variable x, a, y, u, dx, xl, ul, yl : bit8;
wait until start’event and start = ‘1’;
x:=x_port; y:=y_port; a:=a_port; u:=u_port;
dx:=dx_port;
DIFFEQ_LOOP : while (x < a) loop
wait until clock’event and clock = ‘1’;
xl := x+dx;
ul := u-(3*x*u*dx)-(3*y*dx);
yl := y+(u*dx);
x := xl; u := ul; y := yl;
end loop DIFFEQ_LOOP;
y_port <= y;
end process;
end BEHAVIOR;

7. Hardware Description Languages
Verilog
module DIFFEQ (x, y, u, dx, a, clock, start);
input [7:0] a, dx;
inout [7:0] x, y, u;
input clock, start;
reg [7:0] xl, ul, yl;
always
begin
wait (start);
while (x < a)
xl = x +dx;
ul = u - (3*x*u*dx) - (3*y*dx);
yl = y + (u*dx);
@(posedge clock);
x = xl; u = ul; y = yl;
end
endmodule

8. Abstract Model Structure
Can be modeled in terms of incidence structures
modules and/or pins + nets + incidence relation
Hypergraph or bipartite graph m1 n1 n1 m2 m1 n1 m2 n2 n3 n2 m1 n3 m3 m2 m3 n2 m3 n3

9. Netlist: when the corresponding incidence matrix is sparse
Abstract Model
Incidence matrix
Netlist: when the corresponding incidence matrix is sparse
module-oriented, net-oriented
Hierarchy: leaf module is a primitive
n1 n2 n3 m2 m1 m2 m3 n1 n2 m1 n3
m1: n1, n2, n3
m2: n1, n2
m3: n2, n3 m3

10. Logic network Combinational Sequential No feedback (partial order)
Abstract Model
Logic network
Combinational
No feedback (partial order)
Boolean network: multi-input/multi-output, vertex describes multi-input/single-output leaf module.
Sequential
Not necessarily partial order c e e d
d = ab’ + a’b
e = dc’ + d’c
f = dc + ab b f a

11. State diagram A set of primary inputs X A set of primary outputs Y
Abstract Model
State diagram
A set of primary inputs X
A set of primary outputs Y
A set of states S
State transition function d : X  S -> S
Output function l : X  S -> Y (Mealy)
l : S -> Y (Moore)
Initial state

12. Control/data-flow graph
Abstract Model
Control/data-flow graph
Data-flow graph
Operations + data dependency 3 x u dx 3 y u dx x dx v1 * * v2 * v6 * + v8
v10 y xl dx a v7 +
< v3 * *
v11 u v9 - v4 yl c - v5
xl = x +dx;
ul = u - (3*x*u*dx) - (3*y*dx);
yl = y + (u*dx);
c = xl < a; ul

13. * + - < Control-flow graph Control/Data-Flow Graph (CDFG)
Abstract Model
Control-flow graph
Conditional branching, iteration, model call
Control/Data-Flow Graph (CDFG)
How to merge the two graphs
Simple approach: data-flow graph + branching vertices
Sequencing graph
Hierarchical CDFG
Vertices: operations, links
Acyclic (partial order)
Polar: source and sink
model no operation
Link vertex: model call,
branching,
iteration
NOP * + -
< v0 v1 v2 v6 v3 v4 v7 v8
v10
v11 v9 v5 vn

14. Model call x = a * b; y = x * c; z = a + b; submodel(a, z)
Abstract Model
Model call
x = a * b;
y = x * c;
z = a + b;
submodel(a, z)
submodel(m, n) {
p = m + n;
q = m * n; }
NOP * + *
CALL
NOP
NOP + *
NOP

15. Branching x = a * b y = x * c z = a + b if (z ³ 0) { p = m + n;
Abstract Model
Branching
x = a * b
y = x * c
z = a + b
if (z ³ 0) {
p = m + n;
q = m * n; }
NOP * + * BR
NOP
NOP
NOP + *
NOP
NOP
NOP

16. Iteration diffeq { read (x, y, u, dx, a); repeat { xl = x + dx;
Abstract Model
Iteration
diffeq {
read (x, y, u, dx, a);
repeat {
xl = x + dx;
ul = u - (3*x*u*dx) - (3*y*dx);
yl = y + (u*dx);
c = xl < a;
x = xl; u = ul; y = yl;
} until (c);
write (y); }
NOP
READ
LOOP
LOOP BODY
WRITE
NOP

17. Delay Data independent Data dependent
Abstract Model
Delay
Data independent
Data dependent
Bounded (min., max.): loop, conditional branch
Unbounded: external synchronization
Latency: overall delay of a graph
Bounded-latency graph
Unbounded-latency graph
NOP * + BR

18. Compilation and Behavioral Optimization
Hardware compiler vs. software compiler
front end
intermediate form
back end
machine
code
lex
parse
optimization
codegen
front end
intermediate form
back end
a-synthesis
mask
layout
behavioral
optimization
l-synthesis
lex
parse
P&R

19. Compilation and Behavioral Optimization
on parse tree and CDFG
front end
parse tree
behavioral
optimization
control/data-flow
analysis
CDFG
back end

20. Compilation and Behavioral Optimization
Data-flow-based transformation
Tree height reduction + + + + * * a b c d a d b c
(a + (b * c)) + d
(a + d) + (b * c)

21. Compilation and Behavioral Optimization+ * + * * * * * * a b c d e a b c d a e
a * (b * c * d + e)
(a * b) * (c * d) + a * e

22. Compilation and Behavioral Optimization
Constant propagation
a = 0; a = 0;
b = a + 1; > b = 1;
c = 2 * b; c = 2;
Variable propagation
a = x; a = x; can be removed
b = a + 1; > b = x + 1;
c = 2 * a; c = 2 * x;
Common subexpression elimination
a = x + y; a = x + y;
b = a + 1; > b = a + 1;
c = x + y; c = a;
Dead code elimination
a = x; can be removed
b = x + 1;
c = 2 * x;

23. Compilation and Behavioral Optimization
Operator strength reduction
a = x2 ; a = x * x;
b = 3 * x; > t = x << 1;
b = x + t;
Code motion (hoisting)
for (i = 1; i <= a * b; i++) {...} ---> t = a * b;
for (i = 1; i <=t; i++) {...}
Code motion (lowering)
z1 = x + y; if (c = 1) {
z2 = x - y; z1 = x + y;
if (c = 1) { a = f (z1);
a = f (z1); > }
} else {
else { z2 = x - y;
b = f (z2); b = f (z2);
} }

24. Compilation and Behavioral Optimization
Control-flow-based transformation
Model expansion
x = a + b; x = a + b;
y = a * b; ---> y = a * b;
z = foo (x, y); z = y - x;
foo (p, q) {
t = q - p;
return t; }
Conditional expansion
y = ab; y = ab;
if (a) x = b + d; > x = y + d (a + b);
else x = bd;
x = a(b + d) + a’bd; = ab + ad + a’bd; = ab + ad + abd + a’bd;
= ab + ad + bd; = ab + d (a + b);

25. Compilation and Behavioral Optimization
Loop expansion (unrolling)
x = 0; x = 0;
for (i = 1; i <= 3; i++) > x = x + a[1];
x = x + a[i]; x = x + a[2];
x = x + a[3];
x = a[1] + a[2] + a[3];