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Ideas for adding FPGA Accelerators to DPDK

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Presentation on theme: "Ideas for adding FPGA Accelerators to DPDK"— Presentation transcript:

1 Ideas for adding FPGA Accelerators to DPDK
Weihua (Rosen) Xu; Tianfei Zhang

2 Legal Disclaimers No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. © 2017 Intel Corporation. Intel, the Intel logo, Intel. Experience What’s Inside, and the Intel. Experience What’s Inside logo are trademarks of Intel. Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others.

3 Agenda Problem Statement Partial Reconfiguration (PR) Use-case
FPGA Acceleration in DPDK Usage Scenario

4 Problem Statement With Partial Reconfigure(PR) parts of Bitstream, Field Programmable Gate Array(FPGA) not only provides one kinds of accelerator but also provides many types of accelerators at the same time How DPDK fully support FPGA? Which type of DPDK Device can provide FPGA PR? How can we bind DPDK Driver to FPGA Partial-Bitstream?

5 Partial Reconfiguration (PR) Use-case
FPGA Management SW Need To Partial Reconfigure AFU Image dynamically Currently No Normal DPDK Module Can Take FPGA Control Work Facility For Workload DPDK Driver Based On AFU Device Not FPGA Device Reuse UIO/VFIO Module to Probe FPGA Device Note: FME(FPGA Management Engine): Manage whole FPGA, provide PR Interface AFU(Accelerated Function Unit): Partial-Bitstream Each Acceleration is implemented by AFU

6 OPAE Intro

7 FPGA Acceleration on DPDK
rte_bus_list pci_device_list pci_driver_list constructor pci ifpga mcp_fpga mcp_drv 1 rte_bus_register raw_dev_array afu_list INSERT to rte_bus_list afu_eth rawdev.ops dev_fpga ENUMERATE & PR INSERT AFU Device 2 rte_ifpga_driver_register afu_driver_list INSERT to afu_driver_list rte_eal_hotplug_add drv_eth PROBE AFU Driver Rawdev probed as PCI Driver takes FPGA Configuration(Download/PR) 2 scans FPGA PCI Scan(1st Scan) follows DPDK UIO/VFIO PCI Scan Process AFU Scan(2nd Scan) bind DPDK Driver to FPGA Partial-Bitstream OPAE Provides Common lib and API for low level FPGA management & accelerator access

8 Bare Metal: Dedicated for User-Space Usage
DPDK Device PMD For defined DPDK Device(Ethdev/Cryptodev/Eventdev) Non-DPDK User-Space Driver For Customized Device, Transparent DPDK Rawdev Support PR Rawdev is submited in 18.02 Note: DPDK and NON-DPDK mode will not run at the same time

9 Virtualization: Partial Resource for VM
FPGA Management by OPAE Kernel Driver (Upstream in progress) DPDK in VM with Normal PMD

10 Summary DPDK with OPAE for full FPGA support 2 scans
PCI bus: Rawdev for FPGA configuration FPGA bus: AFU scan for device driver binding Support both bare metal and virtualization

11 Thanks!


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