1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. Decoders and Encoders CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff HW 6 is out It is due on Monday (Oct 14) Wednesday (Oct 16)

4. Administrative Stuff HW 7 is out It is due next Monday (Oct 21)

5. Administrative Stuff Midterm Grades are Dues this Friday only grades of C-, D, F have to be submitted to the registrar’s office

6. Administrative Stuff Midterm Exam #2 When: Monday October 28. Where: This classroom What: Chapters 1, 2, 3, 4 and 5.1-5.4 The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).

7. Quick Review

8. Graphical Symbol for a 2-1 Multiplexer f s x 1 x 2 0 1 [ Figure 2.33c from the textbook ]

9. Circuit for 2-1 Multiplexer f x 1 x 2 s f s x 1 x 2 0 1 (c) Graphical symbol (b) Circuit [ Figure 2.33b-c from the textbook ] f (s, x 1, x 2 ) = s x 1 s x 2 +

10. 4-to-1 Multiplexer: Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

11. 0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer [ Figure 4.3 from the textbook ]

12. w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f 16-1 Multiplexer [ Figure 4.4 from the textbook ]

13. Synthesis of Logic Circuits Using Multiplexers

14. Implementation of a logic function with a 4x1 multiplexer [ Figure 4.6a from the textbook ] f w 1 0 1 0 1 w 2 1 0 0 0 1 1 1 0 1 fw 1 0 w 2 1 0

15. Implementation of the same logic function with a 2x1 multiplexer [ Figure 4.6b-c from the textbook ] (b) Modified truth table 0 1 0 0 1 1 1 0 1 fw 1 0 w 2 1 0 f w 2 w 1 0 1 f w 1 w 2 w 2 (c) Circuit

16. The XOR Logic Gate [ Figure 2.11 from the textbook ]

17. The XOR Logic Gate

18. Implemented with a multiplexer f

19. The XOR Logic Gate Implemented with a multiplexer x y f

20. The XOR Logic Gate Implemented with a multiplexer x y f These two circuits are equivalent (the wires of the bottom and gate are flipped)

21. In other words, all four of these are equivalent! x y f x y f x y f f w 1 0 1 w 2 1 0

22. Another Example (3-input XOR)

23. [ Figure 4.8a from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1

24. [ Figure 4.8a from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 2 w 3  w 2 w 3 

25. [ Figure 4.8 from the textbook ] Implementation of 3-input XOR with 2-to-1 Multiplexers (a) Truth table 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 2 w 3  w 2 w 3  f w 3 w 1 (b) Circuit w 2

26. 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9a from the textbook ]

27. 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9a from the textbook ]

28. f w 1 w 2 (a) Truth table (b) Circuit 00 01 10 11 0 1 1 0 00 01 10 11 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 w 3 Implementation of 3-input XOR with a 4-to-1 Multiplexer [ Figure 4.9 from the textbook ]

29. Multiplexor Synthesis Using Shannon’s Expansion

30. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 Three-input majority function [ Figure 4.10a from the textbook ]

31. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 0 1 f w 1 Three-input majority function [ Figure 4.10a from the textbook ]

32. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 0 1 f w 1 w 2 w 3 w 2 w 3 + Three-input majority function [ Figure 4.10a from the textbook ]

33. 00 01 10 11 0 0 0 1 00 01 10 11 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 (b) Circuit 0 1 f w 1 w 2 w 3 w 2 w 3 + f w 3 w 1 w 2 (b) Truth table Three-input majority function [ Figure 4.10 from the textbook ]

34. Three-input majority function f w 3 w 1 w 2

35. Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:

36. Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form:

37. Shannon’s Expansion Theorem Any Boolean function can be rewritten in the form: cofactor

38. Shannon’s Expansion Theorem (Example)

39. Shannon’s Expansion Theorem (Example) (w 1 + w 1 )

40. Shannon’s Expansion Theorem (Example) (w 1 + w 1 )

41. Shannon’s Expansion Theorem (In terms of more than one variable) This form is suitable for implementation with a 4x1 multiplexer.

42. Another Example

43. Factor and implement the following function with a 2x1 multiplexer

45. w f [ Figure 4.11a from the textbook ]

46. Factor and implement the following function with a 4x1 multiplexer

48. [ Figure 4.11b from the textbook ]

49. Yet Another Example

50. Factor and implement the following function using only 2x1 multiplexers

53. f g h w1w1

56. g 0 w3w3 w2w2 h w3w3 1 w2w2

57. Finally, we are ready to draw the circuit g 0 w3w3 w2w2 h w3w3 1 w2w2 f g h w1w1

58. g 0 w3w3 w2w2 h 1 f w1w1

59. w 2 0 w 3 1 f w 1 [ Figure 4.12 from the textbook ]

60. Decoders

61. 2-to-4 Decoder (Definition) Has two inputs: w 1 and w 0 Has four outputs: y 0, y 1, y 2, and y 3 If w 1 =0 and w 0 =0, then the output y 0 is set to 1 If w 1 =0 and w 0 =1, then the output y 1 is set to 1 If w 1 =1 and w 0 =0, then the output y 2 is set to 1 If w 1 =1 and w 0 =1, then the output y 3 is set to 1 Only one output is set to 1. All others are set to 0.

62. Truth Table and Graphical Symbol for a 2-to-4 Decoder [ Figure 4.13a-b from the textbook ]

63. Truth Logic Circuit for a 2-to-4 Decoder [ Figure 4.13c from the textbook ]

64. Adding an Enable Input [ Figure 4.13c from the textbook ]

65. Adding an Enable Input [ Figure 4.13c from the textbook ] En

66. Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input [ Figure 4.14a-b from the textbook ]

67. Truth Table and Graphical Symbol for a 2-to-4 Decoder with an Enable Input [ Figure 4.14a-b from the textbook ] x indicates that it does not matter what the value of these variable is for this row of the truth table

68. Graphical Symbol for a Binary n-to-2 n Decoder with an Enable Input [ Figure 4.14d from the textbook ] A binary decoder with n inputs has 2 n outputs The outputs of an enabled binary decoder are “one-hot” encoded, meaning that only a single bit is set to 1, i.e., it is hot.

69. How can we build larger decoders? 3-to-8 ? 4-to-16? 5-to-??

70. w 8 w 11 s 1 w 0 s 0 w 3 w 4 w 7 w 12 w 15 s 3 s 2 f Hint: How did we build a 16-1 Multiplexer [ Figure 4.4 from the textbook ]

71. w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 A 3-to-8 decoder using two 2-to-4 decoders [ Figure 4.15 from the textbook ]

72. w 2 w 0 y 0 y 1 y 2 y 3 w 0 En y 0 w 1 y 1 y 2 y 3 w 0 y 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 A 3-to-8 decoder using two 2-to-4 decoders [ Figure 4.15 from the textbook ] What is this?

73. w 0 y 0 y 1 En What is this?

74. A 4-to-16 decoder built using a decoder tree [ Figure 4.16 from the textbook ]

75. Let’s build a 5-to-32 decoder

76. Demultiplexers

77. 1-to-4 Demultiplexer (Definition) Has one data input line: D Has two output select lines: w 1 and w 0 Has four outputs: y 0, y 1, y 2, and y 3 If w 1 =0 and w 0 =0, then the output y 0 is set to D If w 1 =0 and w 0 =1, then the output y 1 is set to D If w 1 =1 and w 0 =0, then the output y 2 is set to D If w 1 =1 and w 0 =1, then the output y 3 is set to D Only one output is set to D. All others are set to 0.

78. A 1-to-4 demultiplexer built with a 2-to-4 decoder [ Figure 4.14c from the textbook ]

79. A 1-to-4 demultiplexer built with a 2-to-4 decoder [ Figure 4.14c from the textbook ] output select lines the four output lines data input line D

80. Multiplexers (Implemented with Decoders)

81. w 1 w 0 w 0 En y 0 w 1 y 1 y 2 y 3 w 2 w 3 f s 0 s 1 1 A 4-to-1 multiplexer built using a 2-to-4 decoder [ Figure 4.17 from the textbook ]

82. Encoders

83. Binary Encoders

84. 2 n inputs w 0 w 2 n 1– y 0 y n1– n outputs A 2 n -to-n binary encoder [ Figure 4.18 from the textbook ]

85. (b) Circuit w 1 w 0 y 0 w 2 w 3 y 1 0 0 1 1 1 0 1 w 3 y 1 0 y 0 0 0 1 0 w 2 0 1 0 0 w 1 1 0 0 0 w 0 0 0 0 1 (a) Truth table [ Figure 4.19 from the textbook ] A 4-to-2 binary encoder

86. Priority Encoders

87. d 0 0 1 0 1 0 w 0 y 1 d y 0 11 0 1 1 1 1 z 1 x x 0 x w 1 0 1 x 0 x w 2 0 0 1 0 x w 3 0 0 0 0 1 [ Figure 4.20 from the textbook ] Truth table for a 4-to-2 priority encoder

88. Questions?

89. THE END