Presentation is loading. Please wait.

Presentation is loading. Please wait.

3. poglavje: Logične funkcije in osnovna digitalna vezja

Published byLetitia Richards Modified over 5 years ago

Similar presentations

Presentation on theme: "3. poglavje: Logične funkcije in osnovna digitalna vezja"— Presentation transcript:

1 3. poglavje: Logične funkcije in osnovna digitalna vezja
Digitalna tehnika 3. poglavje: Logične funkcije in osnovna digitalna vezja Real-Time Systems Laboratory, Institute of Informatics

2 Tri osnovne Boolove funkcije nad logičnimi spremenljivkami
Real-Time Systems Laboratory, Institute of Informatics

3 Postulati (aksiomi) in teoremi
Real-Time Systems Laboratory, Institute of Informatics

4 Postulati (aksiomi) in teoremi
Primer: Real-Time Systems Laboratory, Institute of Informatics

5 Izvedba Boolovih funkcij s stikali
Primera: Real-Time Systems Laboratory, Institute of Informatics

6 Osnovna logična vrata Real-Time Systems Laboratory, Institute of Informatics

7 Osnovna logična vrata Primera:
Real-Time Systems Laboratory, Institute of Informatics

8 Druga logična vrata Real-Time Systems Laboratory, Institute of Informatics

9 Druga logična vrata Real-Time Systems Laboratory, Institute of Informatics

10 Druga logična vrata Real-Time Systems Laboratory, Institute of Informatics

11 Izvedba vezij z NAND vrati
Real-Time Systems Laboratory, Institute of Informatics

12 Kanonične oblike, mintermi, makstermi
Real-Time Systems Laboratory, Institute of Informatics

13 Minimizacija Boolovih funkcij
Vennovi diagrami Real-Time Systems Laboratory, Institute of Informatics

14 Minimizacija Boolovih funkcij
Veitchevi diagrami Real-Time Systems Laboratory, Institute of Informatics

15 Hazardna stanja pri kombinacijskih vezjih
Real-Time Systems Laboratory, Institute of Informatics

16 Izvedba logičnih funkcij s programirljivimi kombinacijskimi vezji
PAL- programirljiva log. polja PLA- programirljive log. mreže Pomnilniki - EPROM Real-Time Systems Laboratory, Institute of Informatics

17 FPGA vezja http://lniv.fe.uni-lj.si/courses/iv/IV-uvod.pdf
Real-Time Systems Laboratory, Institute of Informatics

18 FPGA vezja http://lniv.fe.uni-lj.si/courses/iv/IV-uvod.pdf
Real-Time Systems Laboratory, Institute of Informatics

19 FPGA vezja http://lniv.fe.uni-lj.si/courses/iv/IV-uvod.pdf
Real-Time Systems Laboratory, Institute of Informatics

Download ppt "3. poglavje: Logične funkcije in osnovna digitalna vezja"

Similar presentations

Velos eResearch Bulk Application Training

Velos eResearch Bulk Application Training
Combinational Logic Word Problems

Combinational Logic Word Problems
Programmable Logic PAL, PLA.

Programmable Logic PAL, PLA.
Programmable Logic Devices

Programmable Logic Devices
1 Programmable Logic. 2 Prgrammable Logic Organization Pre-fabricated building block of many AND/OR gates (or NOR, NAND) Personalized by making or breaking.

1 Programmable Logic. 2 Prgrammable Logic Organization Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking.
Appendix A Logic Circuits. Logic circuits Operate on binary variables that assume one of two distinct values, usually called 0 and 1 Implement functions.

Appendix A Logic Circuits. Logic circuits Operate on binary variables that assume one of two distinct values, usually called 0 and 1 Implement functions.
Chapter 6 – Selected Design Topics Part 4 – Programmable Implementation Technologies Logic and Computer Design Fundamentals.

Chapter 6 – Selected Design Topics Part 4 – Programmable Implementation Technologies Logic and Computer Design Fundamentals.
FIGURE 7-24 Memory map for the 8088 interface in Figure 7-22 and decoder in Figure The 64K SRAM is mapped to the address range E0000H to EFFFFH.

FIGURE 7-24 Memory map for the 8088 interface in Figure 7-22 and decoder in Figure The 64K SRAM is mapped to the address range E0000H to EFFFFH.
ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices.

ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices.
Solving Exponential Equations. One-to-One Properties.

Solving Exponential Equations. One-to-One Properties.
/t/ / I d/ /d/ Try Again Go on /t/ / I d/ /d/

/t/ / I d/ /d/ Try Again Go on /t/ / I d/ /d/
9/20/6Lecture 3 - Instruction Set - Al1 Address Decoding for Memory and I/O.

9/20/6Lecture 3 - Instruction Set - Al1 Address Decoding for Memory and I/O.
8/2/2013 Logarithms 1 = 2 log a x Properties of Logarithms Examples 1. log a x 2 = log a (x x) Coincidence ? log b x r = r log b x Power Rule for Logarithms.

8/2/2013 Logarithms 1 = 2 log a x Properties of Logarithms Examples 1. log a x 2 = log a (x x) Coincidence ? log b x r = r log b x Power Rule for Logarithms.
Section 5.6 Laws of Logarithms (Day 1)

Section 5.6 Laws of Logarithms (Day 1)
Microprocessor Address Decoding.

Microprocessor Address Decoding.
Logarithms Logarithmic functions play an important role in science and engineering. The Richter scale is used to measure the strength of Earthquakes and.

Logarithms Logarithmic functions play an important role in science and engineering. The Richter scale is used to measure the strength of Earthquakes and.
Turn in your Quiz!!! Complete the following:. Section 11-5: Common Logarithms The questions are… What is a common log? How do I evaluate common logs?

Turn in your Quiz!!! Complete the following:. Section 11-5: Common Logarithms The questions are… What is a common log? How do I evaluate common logs?
Units within our institution provide interaction between the schools with the organizations among them.

Units within our institution provide interaction between the schools with the organizations among them.
Laws of Logarithms 5.6. Laws of Logarithms O If M and N are positive real numbers and b is a positive number such that b  1, then O 1. log b MN = log.

Laws of Logarithms 5.6. Laws of Logarithms O If M and N are positive real numbers and b is a positive number such that b  1, then O 1. log b MN = log.
OpenEMR: Basic Billing Based on OpenEMR 4.1 Laboratory Informatics Institute January 2014.

OpenEMR: Basic Billing Based on OpenEMR 4.1 Laboratory Informatics Institute January 2014.

Similar presentations

Ads by Google