1. Introduction to CMOS VLSI Design Lecture 5: DC & Transient Response
David Harris
Harvey Mudd College
Spring 2007

2. Outline Pass Transistors DC Response Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation
5: DC and Transient Response

3. Activity 1) If the width of a transistor increases, the current will
increase decrease not change 
2)     If the length of a transistor increases, the current will
increase decrease not change
3)     If the supply voltage of a chip increases, the maximum transistor current will
4)     If the width of a transistor increases, its gate capacitance will
5)     If the length of a transistor increases, its gate capacitance will
6)     If the supply voltage of a chip increases, the gate capacitance of each transistor will
5: DC and Transient Response

4. Activity 1) If the width of a transistor increases, the current will
increase decrease not change 
2)     If the length of a transistor increases, the current will
increase decrease not change
3)     If the supply voltage of a chip increases, the maximum transistor current will
4)     If the width of a transistor increases, its gate capacitance will
5)     If the length of a transistor increases, its gate capacitance will
6)     If the supply voltage of a chip increases, the gate capacitance of each transistor will
5: DC and Transient Response

5. Pass Transistors We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing VDD
5: DC and Transient Response

6. Pass Transistors We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing VDD
Vg = VDD
If Vs > VDD-Vt, Vgs < Vt
Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded “1”
Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
Transmission gates are needed to pass both 0 and 1
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7. Pass Transistor Ckts
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8. Pass Transistor Ckts
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9. DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter
When Vin = 0 -> Vout = VDD
When Vin = VDD -> Vout = 0
In between, Vout depends on
transistor size and current
By KCL, must settle such that
Idsn = |Idsp|
We could solve equations
But graphical solution gives more insight
5: DC and Transient Response

10. Transistor Operation Current depends on region of transistor behavior
For what Vin and Vout are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
5: DC and Transient Response

11. nMOS Operation Cutoff Linear Saturated Vgsn < Vgsn > Vdsn <
5: DC and Transient Response

12. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn
5: DC and Transient Response

13. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn
Vgsn = Vin
Vdsn = Vout
5: DC and Transient Response

14. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vin < Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Vgsn = Vin
Vdsn = Vout
5: DC and Transient Response

15. pMOS Operation Cutoff Linear Saturated Vgsp > Vgsp < Vdsp >
5: DC and Transient Response

16. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
5: DC and Transient Response

17. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
5: DC and Transient Response

18. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
5: DC and Transient Response

19. I-V Characteristics Make pMOS is wider than nMOS such that bn = bp
5: DC and Transient Response

20. Current vs. Vout, Vin
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21. Load Line Analysis For a given Vin: Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in
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22. Load Line Analysis
Vin = 0
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23. Load Line Analysis
Vin = 0.2VDD
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24. Load Line Analysis
Vin = 0.4VDD
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25. Load Line Analysis
Vin = 0.6VDD
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26. Load Line Analysis
Vin = 0.8VDD
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27. Load Line Analysis
Vin = VDD
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28. Load Line Summary
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29. DC Transfer Curve Transcribe points onto Vin vs. Vout plot
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30. Operating Regions Revisit transistor operating regions Region nMOS
pMOS A B C D E
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31. Operating Regions Revisit transistor operating regions Region nMOS
pMOS A
Cutoff
Linear B
Saturation C D E
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32. Beta Ratio If bp / bn  1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter
5: DC and Transient Response

33. Noise Margins
How much noise can a gate input see before it does not recognize the input?
5: DC and Transient Response

34. Logic Levels To maximize noise margins, select logic levels at
5: DC and Transient Response

35. Logic Levels To maximize noise margins, select logic levels at
unity gain point of DC transfer characteristic
5: DC and Transient Response

36. Transient Response DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations
Input is usually considered to be a step or ramp
From 0 to VDD or vice versa
5: DC and Transient Response

37. Inverter Step Response
Ex: find step response of inverter driving load cap
5: DC and Transient Response

38. Inverter Step Response
Ex: find step response of inverter driving load cap
5: DC and Transient Response

39. Inverter Step Response
Ex: find step response of inverter driving load cap
5: DC and Transient Response

40. Inverter Step Response
Ex: find step response of inverter driving load cap
5: DC and Transient Response

41. Inverter Step Response
Ex: find step response of inverter driving load cap
5: DC and Transient Response

42. Inverter Step Response
Ex: find step response of inverter driving load cap
5: DC and Transient Response

43. Delay Definitions tpdr: tpdf: tpd: tr: tf: fall time
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44. Delay Definitions tpdr: rising propagation delay
From input to rising output crossing VDD/2
tpdf: falling propagation delay
From input to falling output crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
From output crossing 0.8 VDD to 0.2 VDD
5: DC and Transient Response

45. Delay Definitions tcdr: rising contamination delay
From input to rising output crossing VDD/2
tcdf: falling contamination delay
From input to falling output crossing VDD/2
tcd: average contamination delay
tpd = (tcdr + tcdf)/2
5: DC and Transient Response

46. Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write, may hide insight
5: DC and Transient Response

47. Delay Estimation We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask “What if?”
The step response usually looks like a 1st order RC response with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
Depends on average current as gate switches
5: DC and Transient Response

48. Effective Resistance Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay
5: DC and Transient Response