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UC Berkeley Par Lab 1 Technology Trends: The Datacenter is the Computer, The Cellphone/Laptop is the Computer David Patterson Director, Reliable Adaptive.

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Presentation on theme: "UC Berkeley Par Lab 1 Technology Trends: The Datacenter is the Computer, The Cellphone/Laptop is the Computer David Patterson Director, Reliable Adaptive."— Presentation transcript:

1 UC Berkeley Par Lab 1 Technology Trends: The Datacenter is the Computer, The Cellphone/Laptop is the Computer David Patterson Director, Reliable Adaptive Distributed Lab Director, Parallel Computing Lab Past President, ACM October, 2007

2 2 Outline LAN: 10X BW / link / 4-5 years Internet: Data Centers = new Internet backbone DRAM: 2X size / chip / 3 years, = latency, > BW Larger % chips, % power, % $ of systems Flash: Threat to (small) disks? Disk: 2X size / disk / 3 years, = latency, > BW CPU: 2X cores / chip / 2 years, clock rate, = power Cell phone/Laptop and Datacenter: Ends of spectrum most interesting platforms of future?

3 3 Technology Trends: LAN Ethernet: from shared media to switch and twisted pair shortens time to new generation –But shorter distance per link using copper Year of Standard 1983 10 Mbit/s IEEE 802.3 1995 100 Mbit/s IEEE 802.3u 1999 1000 Mbit/s IEEE 802.3ab 2003 10000 Mbit/s IEEE 802.3ac (optical) 2006 10000 Mbit/s IEEE 802.3an (copper) Expect 10 Gbit/s economical in 2007 100 Gbit/sec IEEE standard started 2006 –Standard in 2008? Economical in 2012?

4 4 Technology Trends: Internet Datacenters: new Internet backbone –Huge concentration of bandwidth & computation –Shift in traffic pattern More and more traffic is host Datacenter Huge data transfers between/within DCs are the norm Note: IP alone not designed for such networks

5 5 Technology Trends: DRAM DRAM capacity: decelerate capacity per chip due in part to 32-bit address limit, investments –512 Mbit sold in 2002; still dominates as of Jan 07 –2X capacity every 3 years? (vs. 4X/3yrs in 1990s) –DRAM performance: only BW improvements (DDR-2, DDR-3), little latency improvement, power worse 64-bit Addresses + Multiple cores/socket Majority % chips DRAM vs. Logic Majority % of power is DRAM vs. Logic Majority % of system $ DRAM vs. Logic Shift in % chips, power, $ to DRAM from CPU and % increases over time

6 6 Technology Trends: Disk Disk: After capacity 100% per year 96 - 03, slowdown recently: 30%? 50%? (1TB in 07) –Consolidation of industry, lack of demand by PCs –Home Video restart PC demand, capacity wars? Split: ATA best GB/$, SCSI best performance/$ –Reliability close (see 2007 Google and CMU papers) Performance: Interface switch from parallel to serial: Serial ATA (SATA), Serial SCSI (SAS) Low Cost Disk arrays Disk performance: latency slow change, bandwidth improves, but not as fast as capacity Takes longer to read whole disk (3 hours) Takes longer repair Must handle 2 faults RAID 6 or 3X replication (power, space?)

7 7 Technology Trends: Flash Flash Memory is credible threat to small disks –Modular, 1000X latency, BW, < power, but 1M writes Camera, Ipod industry funds flash R&D –Flash Improvement Rate: 2X GB/$ every 9 months? IF disk and flash rates continue, flash matches GB/$ SCSI in 2009, GB/$ SATA in 2012 Future: Phase-change RAM (PRAM); no write limit, write 30X faster, archival; Samsung 2008? 2007SATASCSIFlashDRAM GB/$3.330.500.080.01 IOPS/GB0.242005,000,000 GB/Watt5051000.5

8 8 A Parallel Revolution PC, Server: Power Wall + Memory Wall = Brick Wall End of way built microprocessors for last 40 years New Moores Law is 2X processors (cores) per chip every technology generation ( 2 years), but same (or slower) clock rate and simpler CPUs –Conservative plan: 2007 4 cores/chip, 2009 8 cores, 2011 16 cores, … for laptop & server & embedded –This shift toward increasing parallelism is not a triumphant stride forward based on breakthroughs; actually a retreat from even greater challenges that thwart efficient silicon implementation of traditional solutions. The Parallel Computing Landscape: A Berkeley View, Dec 2006 Sea change for HW & SW industries since changing the model of programming and debugging Every program(mer) is a parallel program(mer), Sequential algorithms are slow algorithms Par Lab

9 9 100+ Cores? 5-year research program aim 8+ years out Multicore: 2X / 2 yrs 64 cores in 8 years Manycore: 8X multicore Par Lab 80x86 Uniprocessors No longer sold 16-way MP laptops for sale in 2011

10 10 Revolution May Fail John Hennessy, President, Stanford University, 1/07: …when we start talking about parallelism and ease of use of truly parallel computers, we're talking about a problem that's as hard as any that computer science has faced. … I would be panicked if I were in industry. A Conversation with Hennessy & Patterson, ACM Queue Magazine, 4:10, 1/07. 100% failure rate of Parallel Computer Companies –Convex, Encore, MasPar, NCUBE, Kendall Square Research, Sequent, (Silicon Graphics), Transputer, Thinking Machines, … What if IT goes from a growth industry to a replacement industry? –If SW cant effectively use 8, 16, 32,... cores per chip SW no faster on new computer Only buy if computer wears out Accelerate trend to SaaS? Par Lab

11 11 Re-inventing Client/Server Laptop/Handheld as future client, Datacenter as future server The Datacenter is the Computer Building sized computers: Google, MS, … The Laptop/Handheld is the Computer 2007: HP sales laptops > desktops 1B+ Cell phones/yr, increasing in function Apple iPhone raises the bar for quality and business for cellphones Par Lab

12 12 Trends Summary CPU: 2X cores / chip / 2 years, clock rate, = power (La-Z-boy programmer era is over) DRAM: 2X size / chip / 3 years, = latency, > BW Larger % chips, % power, % $ of systems Flash: Threat to (small) disks? Disk: 2X size / disk / 3 years, = latency, > BW LAN: 10X BW / link / 4-5 years Internet: Data Centers = new Internet backbone Cell phone/Laptop and Datacenter: Ends of spectrum most interesting platforms of future? Par Lab


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