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Design of benchmark circuit s5378 for reduced scan mode activity

Published byΑρκάδιος Κακριδής Modified over 5 years ago

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Presentation on theme: "Design of benchmark circuit s5378 for reduced scan mode activity"— Presentation transcript:

1 Design of benchmark circuit s5378 for reduced scan mode activity
Nelson Sunwoo

2 objective Modify s5378 to full scan design
Modify scan flip flops to prevent switching in combination logic Compare average power consumption of original and enhanced design

3 Problem with testing Scan shift causes redundant switching in combination logic. Power dissipation during the test mode is up to three times higher than normal mode.

4 Original circuit . . . Scan Flip Flop SO D mux DFF 1 Q SI SE
Combinational logic Scan flip- flops Primary inputs outputs SI SO SE D Q Scan Flip Flop Scan flip- flops Scan flip- flops DFF mux SE SI D Q SO 1 Scan flip-flop . . .

5 Original circuit simulation

6 Modified circuit

7 Modified circuit simulation

8 Power analysis technology: TSMC 0.18um Vdd: 1.8V clock speed: 1GHz 1000 random vector sets - inputs (0.5 activity) - Scan in (random)

9 simulation

10 result Original design Modified design Power reduction Average Power
52.559mW 36.252mW 31 %

11 reference S. Gerstendrfer and H. J. Wunderlich, Minimized Power Consumption for Scan-based BIST, International Test Conference, 1999, pp

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