1. VLSI Programming 2IMN35 Lab 2 Questionnaire
Student name 1
Student name 2

2. Fill-in/replace entries in the tables with answers to the questions
Q1: What is the maximum sample frequency of the design according to the synthesis report? Q2: What is the maximum sample frequency of the design according to the static timing report? Compare this with your answer to the previous question. Q3: What did you do to obtain the required sample frequency?
max freq
max freq
(un)equal, because ...
Describe procedure here

3. Fill-in/replace entries in the tables with answers to the questions
Q4: How many of the available resources are utilized by your design? Q5: Can you account for all utilized resources? Q6: What is the maximum sample frequency of your design according to the synthesis report after modication?
LUTs
Flip flops
BRAMs
DSP
other?
....
.....%
LUTs
Y/N
explanation
FFs
BRAMs
DSP
max freq

4. Fill-in/replace entries in the tables with answers to the questions
Q7: What is the maximum sample frequency of the design according to the static timing report after adding the constraints? Compare this with your answer to the question 2? Q8: Find out what the maximum sample frequency of the design is, by tightening the constraints in 0.5ns steps. Note that the time it takes to run the Place & Route process increases as the constraints are tightened? Q9: Is it possible to get a higher sample frequency than indicated by the synthesis report?
max freq
(un)equal, because ...
max freq
@ constraint value
Y/N, because ...