Chad Nickell Sean Martin Chris Rothe Daniel Shay

Chad Nickell Sean Martin Chris Rothe Daniel Shay
AMPLINE Chad Nickell Sean Martin Chris Rothe Daniel Shay 12/3/2018 Nickell, Martin, Rothe, Shay

Presentation Overview
System Overview Core Motor Assembly Receiver/Transmitter Hardware Software algorithms Administrivia Progress Schedule Tasks Division of labor 12/3/2018 Nickell, Martin, Rothe, Shay

Nickell, Martin, Rothe, Shay
Description The Ampline System will locate a hockey puck and control a tripod to follow it with a camera. 12/3/2018 Nickell, Martin, Rothe, Shay

System Overview Camera Tripod Transmitter Motors Core Control Receiver 12/3/2018 Nickell, Martin, Rothe, Shay

Core System - Objectives
Get data from receivers Process data Output camera movement data 12/3/2018 Nickell, Martin, Rothe, Shay

Core System - Implementation
Motorola 68HC000 Processor Xilinx Spartan XCS10 FPGA 74LS244 Bus Drivers 74LS245 Bus Transceivers 27C512 EPROMs (2 x 64 kB) 2 x 128 kB SRAM ECS MHz Clock Power Circuitry LM7805 5V Regulator LM V Regulator 12/3/2018 Nickell, Martin, Rothe, Shay

12/3/2018 Nickell, Martin, Rothe, Shay

Core System - Processor
Motorola 68HC000 Processor Xilinx Spartan XCS10 FPGA 74LS244 Bus Drivers 74LS245 Bus Transceivers 27C512 EPROMs (2 x 64 kB) 2 x 128 kB SRAM ECS MHz Clock Power Circuitry LM7805 5V Regulator LM V Regulator 12/3/2018 Nickell, Martin, Rothe, Shay

Core System - Memory Motorola 68HC000 Processor Xilinx Spartan XCS10 FPGA 74LS244 Bus Drivers 74LS245 Bus Transceivers 27C512 EPROMs (2 x 64 kB) 2 x 128 kB SRAM ECS MHz Clock Power Circuitry LM7805 5V Regulator LM V Regulator 12/3/2018 Nickell, Martin, Rothe, Shay

Memory Map 12/3/2018 Nickell, Martin, Rothe, Shay

Core System - FPGA Motorola 68HC000 Processor Xilinx Spartan XCS10 FPGA 74LS244 Bus Drivers 74LS245 Bus Transceivers 27C512 EPROMs (2 x 64 kB) 2 x 128 kB SRAM ECS MHz Clock Power Circuitry LM7805 5V Regulator LM V Regulator 12/3/2018 Nickell, Martin, Rothe, Shay

FPGA Contents Boundary Scan Block to allow reprogramming Microprocessor Handshaking Logic Motor Control Logic 12/3/2018 Nickell, Martin, Rothe, Shay

Core System - Power Motorola 68HC000 Processor Xilinx Spartan XCS10 FPGA 74LS244 Bus Drivers 74LS245 Bus Transceivers 27C512 EPROMs (2 x 64 kB) 2 x 128 kB SRAM ECS MHz Clock Power Circuitry LM7805 5V Regulator LM V Regulator 12/3/2018 Nickell, Martin, Rothe, Shay

Camera Tracking System
Controlled my commands from μp Use stepper motors to control horizontal and vertical angle Mounted on an available tripod Gearing tailored to the angular response requirements 12/3/2018 Nickell, Martin, Rothe, Shay

Camera Tripod - Stepper Motors
One Stepper motor with a threaded shaft to control vertical movement One Stepper motor mounted vertically to control horizontal motion 12/3/2018 Nickell, Martin, Rothe, Shay

Camera Tripod - Stepper Control
H bridge chips UC3770 or UC3717 with protection diodes For Bipolar Motors we will use a total of two chips. Logic built into the FPGA Memory map control commands Timing offloaded to FPGA Reduce μP load 12/3/2018 Nickell, Martin, Rothe, Shay

Camera Tripod - Motor Driver

Camera Tripod - Power Motors require voltages in the range of 12 VDC Current up to 2 amps Noise problems require that steppers isolated from the microprocessor DC-DC Converter or separate transformer 12/3/2018 Nickell, Martin, Rothe, Shay

RF RX/TX No go - phased array, or wave guide arrays too expensive and difficult Transmitter would require too much RF power (1 mW) Alternatives: Ultrasound, IR, Vision Recognition 12/3/2018 Nickell, Martin, Rothe, Shay

Ultrasonic – RX/TX Many advantages Cheap transducers Slower Wave propagation Algorithm Easier to implement As few as 4 receivers required for operational system More Support Scare the rats away 12/3/2018 Nickell, Martin, Rothe, Shay

Locator Algorithm Ultrasonic Pulse arrives at each receiver at different times Use the speed of sound as a constant to determine distance 12/3/2018 Nickell, Martin, Rothe, Shay

Ultrasonic Timing Diagram
Transmitter sends pulse Transmitter sends 2nd pulse First receiver gets pulse Last receiver gets pulse Time = 0 T1 T2 T3 T4 T5 Time = 50ms Processing and Camera Movement Done 12/3/2018 Nickell, Martin, Rothe, Shay

Ultrasonic Receiver Module
Amplifier (High Gain Op Amp) Comparator Receiver Core Board 12/3/2018 Nickell, Martin, Rothe, Shay

Ultrasonic Transmitter Module
Timer (50 ms) Amplifier Ultrasonic Transmitter 12/3/2018 Nickell, Martin, Rothe, Shay

Software Requirements
Monitor Program for development and debugging Software Executive to interface the distance calculations and camera control Camera Control Drivers Distance Algorithm 12/3/2018 Nickell, Martin, Rothe, Shay

Monitor Program Load into SRAM and execute code Minimize the code space Use S records 12/3/2018 Nickell, Martin, Rothe, Shay

Software Executive Main Loop no OS Simple This is a task specific machine Subtasks Find position Determine position relative to current camera location Command the camera tracker to acquire the target 12/3/2018 Nickell, Martin, Rothe, Shay

Camera Control Drivers
Memory Map the control of the camera pointing Maintain Memory of Current Location Variable speed actuation Multiple Directions 12/3/2018 Nickell, Martin, Rothe, Shay

Distance Algorithm -If R1 is at the origin, the length of (T,R2) segment, assuming speed of sound fixed, is d+cDt. -Using the law of cosines, (d+cDt) 2 = z2+d2-2zdcosa d2+2dcDt+(cDt) 2 = z2+d2-2zdcosa d(2cDt+2zcosa) = z 2 -(cDt) 2 12/3/2018 Nickell, Martin, Rothe, Shay

Progress Report μP board wired w/ exception of serial port and peripherals Board Runs Code From EPROM Memory Test Working Parts Ordered 12/3/2018 Nickell, Martin, Rothe, Shay

Problems Encountered BSCAN block was not included in Xilinx Schematics so FPGA could not be reprogrammed Bus Driver was not working Handshaking Logic was incorrectly specified IPLO, BERR, BGACK, VPA needed to be pulled up to VCC 12/3/2018 Nickell, Martin, Rothe, Shay

Schedule 12/3/2018 Nickell, Martin, Rothe, Shay

Current Tasks Spoke with Professor Kuester to finalize and help clear up RF design Decided on an Ultrasonic design Finished Testing EPROM and RAM to ensure correct functionality and interface with M68k Construct Serial Port on Board Begin testing and prototyping Ultrasonic design Begin testing and prototyping Motor Design 12/3/2018 Nickell, Martin, Rothe, Shay

Parts List/Costs Main Board Description Price Quantity Total Board $ $10 Processor Motorola 68k $ $0 EPROM Fairchild 27C512 $ $0 EPROM AMD 27C512 $ $0 RAM Samsung K6T1008 $ $0 FPGA Spartan XCS10 $ $0 Multi Function Peripheral MC $ $0 Standoffs $ $2 Motor Control Stepper Motors SMT-63 $ $5.50 Gears GR-5 $ $2.75 Stepper Motor Driver UC3770BN $ $0 Transmitter/Receiver Ultrasonic RX/TX Pair $ $25.00 Total $45.25 12/3/2018 Nickell, Martin, Rothe, Shay

Division of Labor Chad Motor Control Feedback vs. Memory Motor Power Daniel Core microprocessor Serial / Peripherals Mechanical design of tripod PCB – Ultrasonic Receivers Prototype Verification Sean Lead software development Ultrasonic Coding Motor Drivers Transmitter/Receiver Integration and Test Chris Core microprocessor Design and Prototype 12/3/2018 Nickell, Martin, Rothe, Shay

Questions 12/3/2018 Nickell, Martin, Rothe, Shay

“Thank You, Thank You, Thank You…” –Dave Kelly

Chad Nickell Sean Martin Chris Rothe Daniel Shay

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