1. ADC32RF45 Testing

2. Hardware Setup
Connect the ADC to the left FMC HPC connector on the KCU105 (see Figure on next slide).
Connect an external source to ADC_CLK_IN (J5) of the ADC32RF45EVM.
Connect an external source to LMK_CLKIN (J7) of the ADC32RF45EVM. This source must be synchronized with the ADC_CLK_IN source.
Connect an external source to SMA AINP (J2) or SMA BINP (J3) of the ADC32RF45EVM.
Connect the power cables to the KCU105 and ADC32RF45EVM.
Connect two USB micro B cables between the KCU105 and a host computer with Vivado loaded: one between the USB to JTAG interface J1, and the other between the dual USB-UART port J4.
Connect an Ethernet cable between the KCU105 and host PC.

3. ADC32RF45 & KCU105 Setup

4. Test Setup:
Single tone is given as input to the device.
Test conditions:
Fs = external 3GHz
Fin = 400MHz
LMK = external 3GHz, clock dist mode
Mode = 82820, 12 bit
Ref clock = 200MHz
Lane Rate 8Gbps

5. Setup Quick Setup page as shown below. Click on “Program EVM”

6. Click on ADC32RFxx tab. Change the De-emphasis to 0 dB for all 8 lanes

7. LMK04828 Clock Outputs tab, set the CLKout 2 and 3 DCLK Type to “Powerdown”.

8. KCU105 Setup
The KCU105 development board uses Ethernet and dual USB-to-UART capabilities to interface with a host computer and set up the FPGA correctly. To program the FPGA firmware, the bit file must be loaded using the Xilinx Vivado design tool. The first step will be to establish communication with the KCU105 board.
Open a serial port connection with any sort of serial terminal software, e.g. TeraTerm, Hercules, etc.
Initialize a serial port communication to Silicon Labs Dual CP210x USB to UART Bridge: Enhanced COM Port.
Click on “Setup” then select “Serial Port”. Set the baud rate of this serial connection to , and leave all other defaults as set.
Open another serial port connection and connect to Silicon Labs Dual CP210x USB to UART Bridge: Standard COM Port.
Ensure the baud rate of this serial connection is 9600, leaving all other defaults as set.

9. KCU105 setup (cont.)
Power up the KCU105 board. There should be information scrolling on the Enhanced COM port.
Program the FPGA, doing the following steps:
Open Xilinx Vivado design tool
Double click on “Open Hardware Manager”.
Click on “Open Target”, and select “Open New Target”
Click on “Next” twice. Select the Hardware Target, and click “Next” again.
Click on “Finish”.
Click on “Program device”. Select xcku040_0.
Navigate to the provided bit file for the project.
Select the proper bit file: “KC105_TI_DHCP.bit.”
Click on “Program device”.
A new window will open showing the status of the programming. Once this reaches100%, the FPGA is programmed. The board IP address will be available on the Standard COM port.
Next, the VADJ8 voltage must be set to 1.8V. This is set in the Enhanced COM port terminal.
Navigate to the Enhanced COM port window. Return to the main menu by entering “0” in the terminal.
Select “Adjust FPGA Mezzanine Card (FMC) settings” by entering “4”
“Set FMC VADJ to 1.8V” by entering “4”
Return to the main menu by entering “0”
To check this voltage, select “Get the Power Systems Voltages” by entering “2”
Enter “7” to “Get VADJ1D8 voltage.” The voltage should appear above the menu.
Return to main menu by entering “0”

10. HSDC Pro GUI
Open the special provided version of High Speed Data Converter Pro_KC105 GUI by right clicking on the icon and running as administrator.
In the Select Board popup, check “Connect to KCU105.”
Enter the IP address and Port. This can either be selected from the drop down menu or entered manually. Both the IP Address and Port number can be found in the Standard COM port terminal.

11. IP Address and Port, separated by :

12. After the HSDC Pro GUI connects, then select: “ADC32RF45_82820” Enter “3G” for ADC Output Data Rate. The new lane rate and reference clock settings will be as shown below.

13. Click on “Capture”.
Capture results using a 400MHz input tone are shown below