1. Introduction to I/O PAD

2. Outline Introduction to ESD Latchup Issue in CMOS IC
1.8-V I/O Library in UMC Process

3. What is ESD Electrostatic Discharge (ESD)
ESD is one of the most prevalent reliability threats to the semiconductor products, and effective ESD protection solutions are a necessity, not an option, for electronic components/integrated circuits used in analog, digital, power, RF, optoelectronic, and biomedical applications.

4. A Phenomenon of ESD
The threshold voltage for a person feeling a discharge is ~ 3,500 V
*R.H.: Relative Humidity

5. ESD Threat on IC Products
About 95% of microchips used in electronic systems (cellphones, computers, etc.) require ESD protection…
ESD-induced damages

6. Component-level ESD Issue
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)
Component-level ESD
(JESD22)

7. Component-level ESD Issue
Comparison of HBM, MM, and CDM pulse

8. ESD Spec. for IC Products
Component-level ESD Test
Type
HBM MM
CDM
Okay
+/- 2kV
+/- 200V
+/- 1kV
Safe
+/- 4kV
+/- 400V
+/- 1.5kV
Super
+/- 10kV
An IC during ESD test with all pin combinations has to pass above ESD specifications. (Both positive and negative ESD voltages).

9. ESD Testing on IC Products
Component-level ESD Test
Example: ESD stress on a CMOS IC in HBM/MM Testing
Positive-to-VSS (PS-mode)
Negative-to-VSS (NS-mode)
Positive-to-VDD (PD-mode)
Negative-to-VDD (ND-mode)

10. ESD Testing on IC Products
Component-level ESD Test
Example: ESD stress on a CMOS IC in HBM/MM Testing
Pin-to-Pin (Positive)
Pin-to-Pin (Negative)

11. ESD Testing on IC Products
Component-level ESD Test
Example: ESD stress on a CMOS IC in HBM/MM Testing
VDD-to-VSS (Positive)
VDD-to-VSS (Negative)

12. On-Chip ESD Protection
Typical design of on-chip ESD protection circuits in a CMOS IC

13. ESD Protection Design for I/O Pins

14. Device Issue for ESD Robustness
Enhanced NMOS
Standard NMOS
Silicide blocking and extended drain

15. Layout Parameters to the MOS as ESD Protection Device
0.18um UMC Process ESD Design Rules
Silicide blocking (SAB)

16. Layout of CMOS Device for ESD Protection
The Finger-type of an NMOS device with ESD rule.

17. Latchup Issue in CMOS IC
The Cross-sectional View
Equivalent Circuit
PMOS
NMOS
The latchup structure within PMOS and NMOS in CMOS technology.

18. Diagram of Chip Layout Structure

19. 1.8-V I/O Library in UMC Process
Cell categories
Cell Name
Input Cell
IN_18
Output Cell
OU_18
Power Cell
VDDE_18, VDDI_18,
VSSE_18, VSSI_18
Feeder Cell
Feeder_5u, 10u, 20u, 40u, Corner

20. Whole-Chip ESD Protection Scheme

21. Whole-Chip ESD Protection Scheme

22. CMOS IC with ESD Protection I/O Cells
Internal
Circuits

23. Unit Design IN_18 IN VDDE Mp Rp Rn VSSE Mn PAD (1kΩ) (480μm/0.4μm)

24. Unit Design OU_18 OUT VDDE Mp Rp Rn VSSE Mn PAD (1kΩ) (480μm/0.4μm)

25. Unit Design
VDDE_18
VDDE Rn Mn
VSSE
(480μm/0.4μm)
(1kΩ)
PAD

26. Unit Design
VSSE_18
VDDE Rn Mn
VSSE
(480μm/0.4μm)
(1kΩ)
PAD

27. Unit Design
VDDI
VDDI_18
VDDE Rn Mn
VSSE
(480μm/0.4μm)
(1kΩ)
PAD

28. Unit Design
VSSI
VSSI_18
VDDE Rn
(1kΩ) Mn
VSSE
PAD
(480μm/0.4μm)

29. Unit Design
Feeder_5u, 10u, 20u, 40u, and Corner

30. Use I/O Library IO_Lib.gds: the gds file of IO cells
IO_Lib.sp: the subckt file of IO cells