1. UNIT-I An Over View Of 8085 Architecture Of 8086 Microprocessor
Special Functions Of General Purpose Registers
8086 Flag Register
Function Of 8086 Flags
Addressing Modes Of 8086
Instruction Set Of 8086
Assembler Directives
Procedures And Macros.

2. The salient features of 8085 μp are
• It is an 8 bit microprocessor.
• It is manufactured with N-MOS technology.
• It has 16-bit address bus and hence can address up to 216 = bytes (64KB) memory locations through A0-A15.
• The first 8 lines of address bus and 8 lines of data bus are multiplexed
AD0 –AD7.
• Data bus is a group of 8 lines D0 – D7.
• It supports external interrupt request.
• A 16 bit program counter (PC)
• A 16 bit stack pointer (SP)
• Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
• It requires a signal +5V power supply and operates at 3.2 MHZ
single phase clock.
• It is enclosed with 40 pins DIP (Dual in line package).

3. Fig 1.1 pin diagram of 8085

4. Fig 1.2 Functional Block Diagram of 8085

5. Fig 1.3 Format of 8085 Flag register
Registers
• Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.
• Flag Register has five 1-bit flags.
• Sign - set if the most significant bit of the result is set.
• Zero - set if the result is zero.
• Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
• Parity - set if the parity (the number of set bits in the result) is even.
• Carry - set if there was a carry during addition, or borrow during subtraction/comparison/rotation.
Fig 1.3 Format of 8085 Flag register

6. General Registers
• 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer.
• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.
• 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.

7. Fig 1.4 General purpose registers
• Stack pointer is a 16 bit register. This register is always decremented/incremented by 2 during push and pop.
• Program counter is a 16-bit register
Fig 1.4 General purpose registers

8. An Introduction to 8086 8086 Features 16-bit Arithmetic Logic Unit
• 16-bit data bus
• 20-bit address bus = 1,048,576 = 1 meg
The address refers to a byte in memory. In the 8086, bytes at even addresses come in on the low half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper half of the data bus (bits 8-15).
The 8086 can read a 16-bit word at an even address in one operation and at an odd address in two operations.
The least significant byte of a word on an 8086 family microprocessor is at the lower address.

9. 8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU).
• The BIU fetches instructions, reads and writes data, and computes the 20-bit address.
• The EU decodes and executes the instructions using the 16-bit ALU.

10. • The BIU contains the following registers:
IP - the Instruction Pointer
CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register
The BIU fetches instructions using the CS and IP, written CS:IP, to construct the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode.

11. Fig 1.5 Block Diagram of 8086

12. 8086 Architecture The EU contains the following 16-bit registers:
AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register
SP - the Stack Pointer
BP - the Base Pointer
SI - the Source Index Register
DI - the Destination Register
These are referred to as general-purpose registers, although, as seen by their names, they often have a special-purpose use for some instructions.
Default to stack segment

13. The AX, BX, CX, and DX registers can be considered as two 8-bit registers, a High byte and a Low byte. This allows byte operations and compatibility with the previous generation of 8-bit processors, the 8080 and 8085.
The 8-bit registers are:
AX --> AH,AL
BX --> BH,BL
CX --> CH,CL
DX --> DH,DL

14. 8086 Architecture
The EU also contains the Flag Register which is a collection of condition bits and control bits. The condition bits are set or cleared by the execution of an instruction. The control bits are set by instructions to control some operation of the CPU.
Fig 1.6 Flag Register of 8086

15. Fig 1.7 16-bit Registers of 8086 BIU registers (20 bit adder)ES CS SS DS IP AH BH CH DH AL BL CL DL SP BP SI DI
FLAGS AX BX CX DX
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Register
BIU registers
(20 bit adder)
EU registers
16 bit arithmetic
Fig bit Registers of 8086

16. Fig 1.8 Memory Segmentation of 8086
Segment Starting address is segment register value shifted 4 place to the left.
Address
000000H
MEMORY
EXTRA
64K Data
Segment
64K Code
CODE
STACK
DATA
 CS:0
Segment
Registers
Segments are < or = 64K,
can overlap, start at an address
that ends in 0H.
0FFFFFH
Fig 1.8 Memory Segmentation of 8086

17. Fig 1.9 8086 Memory Terminology
Memory Segments
Segment
Registers
000000H
001000H
DATA
DS:
0100H
10FFFH
0B2000H
SS:
0B200H
STACK
0C1FFFH
0CF00H
ES:
0CF000H
EXTRA
0DEFFFH
0FF00H
CS:
0FF000H
CODE
0FFFFFH
Fig Memory Terminology
Segments are < or = 64K and can overlap.
Note that the Code segment is < 64K since 0FFFFFH is the highest address.

18. Fig 1.10 Physical address calculation in Code Segment
Memory
Segment Register
Offset
Physical or
Absolute Address +
CS: IP
0400H
0056H
4000H
4056H
0400
0056
04056H
CS:IP = 400:56
Logical Address
0FFFFFH
Left-shift 4 bits
Fig 1.10 Physical address calculation in Code Segment
The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.
The physical address is also called the absolute address

19. Fig 1.11 Physical address calculation in Data Segment
Memory
Segment Register
Offset
Physical Address +
DS: EA
05C0
0050
05C00H
05C50H
DS:EA
000000H
0FFFFFH
Fig 1.11 Physical address calculation in Data Segment
Data is usually fetched with respect to the DS register.
The effective address (EA) is the offset.
The EA depends on the addressing mode.

20. Addressing Modes Assembler directive, DW = Define Word
DATA1 DW 25H DATA1 is defined as a word (16-bit) variable, i.e., a memory location that contains 25H.
DATA2 EQU 20H DATA2 is not a memory location but a constant.
Direct Addressing
MOV AX,DATA [DATA1]  AX, the contents of DATA1 is put into AX.
The CPU goes to memory to get data. 25H is put in AX.

21. Immediate Addressing
MOV AX,DATA2 DATA2 = 20H  AX, 20H is put in AX.
Does not go to memory to get data.
Data is in the instruction.
MOV AX, OFFSET DATA1 The offset of SAM is just a number.
The assembler knows which mode to encode by the way the operands SAM and FRED are defined.

22. Register Addressing: MOV AX,BX AX
Register Indirect Addressing:
MOV AX,[BX] AX DS:BX
Can use BX or BP -- Based Addressing (BP defaults to SS)
or DI or SI Indexed Addressing
The offset or effective address (EA) is in the base or index register.
Register Indirect with Displacement: MOV AX,SAM[BX]
AX DS:BX + Offset SAM
Indexed with displacement:
Based with displacement:
Based-Indexed Addressing: MOV AX,[BX][SI] EA = BX + SI
Based-Indexed w/Displacement: MOV AX,SAM[BX][DI]
EA = BX + DI + offset SAM AX
DS:EA
where EA = BX + offset SAM

23. Addressing modes for Branch Related Instructions
NEAR JUMPS and CALLS
Intrasegment
(CS does not change)
Direct -- IP relative displacement
new IP = old IP + displacement
Allows program relocation with
no change in code.
Indirect -- new IP is in memory or a register.
All addressing modes apply.
FAR
Intersegment Direct -- new CS and IP are encoded in
(CS changes) the instruction.
Indirect -- new CS and IP are in memory.
All addressing modes apply
except immediate and register.

24. Assembly Language
The Assembler is a program that reads the source program as data and translates the instructions into binary machine code.
The assembler outputs a listing of the addresses and machine code along with the source code and a binary file (object file) with the machine code.
Most assemblers scan the source code twice -- called a two-pass assembler.
The first pass determines the locations of the labels or identifiers. The second pass generates the code. To locate the labels, the assembler has a location counter. This counts the number of bytes required by each instruction.

25. When the program starts a segment, the location counter is zero.
If a previous segment is re-entered, the counter resumes the count.
The location counter can be set to any offset by the ORG directive.
In the first pass, the assembler uses the location counter to construct a symbol table which contains the offsets or values of the various labels. The offsets are used in the second pass to generate operand addresses.

26. Instruction Set adc Add with carry flag add Add two numbers
and Bitwise logical AND
call Call procedure or function
cbw Convert byte to word (signed)
cli Clear interrupt flag (disable interrupts)
cwd Convert word to doubleword (signed)
cmp Compare two operands
dec Decrement by 1

27. Instruction Set (Contd.)
div Unsigned divide
idiv Signed divide
iret Interrupt return
jmp Unconditional jump
lea Load effective address offset
mov Move data
mul Unsigned multiply
neg Two's complement negate

28. Instruction Set (Contd.)
nop No operation
not One's complement negate
or Bitwise logical OR
out Output (write) to port
pop Pop word from stack
popf Pop flags from stack
push Push word onto stack
pushf Push flags onto stack
ret Return from procedure or function
sal Bitwise arithmetic left shift (same as shl)

29. Instruction Set (Contd.)
sar Bitwise arithmetic right shift (signed)
sbb Subtract with borrow
shl Bitwise left shift (same as sal)
shr Bitwise right shift (unsigned)
sti Set interrupt flag (enable interrupts)
sub Subtract two numbers
test Bitwise logical compare
xor Bitwise logical XOR
j?? Jump if ?? condition met

30. Conditional Jumps Name/Alt Meaning Flag setting
JE/JZ Jump equal/zero ZF = 1
JNE/JNZ Jump not equal/zero ZF = 0
JL/JNGE Jump less than/not greater than or = (SF xor OF) = 1
JNL/JGE Jump not less than/greater than or = (SF xor OF) = 0
JG/JNLE Jump greater than/not less than or = ((SF xor OF) or ZF) =0
JNG/JLE Jump not greater than/ less than or = ((SF xor OF) or ZF) = 1
JB/JNAE Jump below/not above or equal CF = 1
JNB/JAE Jump not below/above or equal CF = 0
JA/JNBE Jump above/not below or equal (CF or ZF) = 0
JNA/JBE Jump not above/ below or equal (CF or ZF) = 1
JS Jump on sign (jump negative) SF = 1
JNS Jump on not sign (jump positive) SF = 0
JO Jump on overflow OF = 1
JNO Jump on no overflow OF = 0
JP/JPE Jump parity/parity even PF = 1
JNP/JPO Jump no parity/parity odd PF = 0
JCXZ Jump on CX =

31. Assembler Directives ASSUME Tells the assembler what segments to use.
SEGMENT Defines the segment name and specifies that the code that follows is in that segment.
ENDS End of segment
ORG Originate or Origin: sets the location counter.
END End of source code.
NAME Give source module a name.
DW Define word
DB Define byte.
EQU Equate or equivalence
LABEL Assign current location count to a symbol.
$ Current location count
DD Define Double Word

32. Procedures
Procedure is a group of instructions used at several different points in a program.
Procedure name PROC arguments
----
RET
ENDP
CALL instruction is used to call a particular procedure
RET instruction at the end of the procedure returns execution to the next instruction
CALL instruction executes, it automatically stores the return address in the stack memory.

33. Passing parameters to procedure
Passing parameters in Registers
DATA SEGMENT
BCD_INPUT DB 20H
BIN_VALUE DB ?
DATA ENDS
CODE SEGMENT
---
MOV AL, BCD_INPUT ;Moving input into AL reg.
CALL BCD_BIN ; call procedure BCD_BIN
NOP
;Procedure to convert BCD to Binary no.
BCD_BIN PROC NEAR
----
RET
BCD_BIN ENDP
CODE ENDS
END

34. Passing parameters in General Memory
DATA SEGMENT
BCD_INPUT DB 20H
BIN_VALUE DB ?
DATA ENDS
CODE SEGMENT
---
CALL BCD_BIN ; call procedure BCD_BIN
NOP
;Procedure to convert BCD to Binary no.
BCD_BIN PROC NEAR
----
MOV AL, BCD_INPUT ;Load input from memory
------
MOV [DI], AL ; Store result in memory
RET
BCD_BIN ENDP
CODE ENDS
END

35. 3. Passing Parameters using Pointers
DATA SEGMENT
BCD_INPUT DB 20H
BIN_VALUE DB ?
DATA ENDS
CODE SEGMENT
---
MOV SI, OFFSET BCD_INPUT ;create pointer to BCD input
MOV DI, OFFSET BIN_VALUE ; Store result
CALL BCD_BIN ; call procedure BCD_BIN
NOP

36. ;Procedure to convert BCD to Binary no
;Procedure to convert BCD to Binary no. BCD_BIN PROC NEAR ---- MOV AL, [SI] ;Load input from memory MOV [DI], AL ; Store result in memory RET BCD_BIN ENDP CODE ENDS END

37. MACROS
A macro is group if instructions we bracket and give a name to at the start of our program. Each time we “call” the macro in our program, the assembler will insert the defined group of instructions in place of the “call”.
Every time a macro name in the program, replace it with the group of instructions defined as that macro at the start of the program. This process is known as expanding the macro or macro expansion.
Using a macro avoids the overhead time involved in calling, returning from a procedure.
A disadvantage of generating in-line code each time a macro is called is that this will make the program take up more memory than using a procedure.

38. Defining a MACRO: Macro_name MACRO dummy parameters ENDM Ex: Move_ASCII MACRO Number,Source,Destination Mov CX,Number ; No. of characters to be moved in CX LEA SI,Source ; Point SI at ASCII source LEA DI,Destination ; Point DI at ASCII destination CLD ; Autoincrement pointer after move REP MOVSB ; Copy ASCII string to new location A macro may be defined in another macro or a macro may be called from inside a macro. This type of macro is called a nested macro.