1. Universal Test Interface for Embedded DRAM TestingBy
Shinji Miyano
Katshhiko Sato
Kenji Numata

2. Contents 1 Testing Dilemma 2 Direct-memory-access mode 3
ThemeGallery is a Design Digital Content & Contents mall developed by Guild Design Inc. 1
Testing Dilemma 2
Direct-memory-access mode 3
Universal Test Interface 4
Self-Burn-In Mode

3. What is the Embedded DRAM?
A capacitor-based dynamic random access memory usually integrated on the same die or in the same package as the main ASIC or processor, as opposed to external DRAM modules and transistor-based SRAM typically used for caches.
eDRAM is used in many game consoles, including the PlayStation 2, PlayStation Portable, Nintendo GameCube, Wii and Xbox 360.

4. A Few Different Product
Testing Dilemma
DRAM
Side
ASIC
Side
Large Market Share
Small Market Share
Embedded
DRAM
A Few Different Product
Large Variety Product

5. Direct-Memory-Access Mode
Wafer test 1 (DRAM)
Fuse Blow
Wafer test 2 (DRAM)
Wafer test 3 (Logic)
Assembly
Burn-in
Test Flow
For Embedded DRAM
Final test (DRAM & Logic)

6. DRAM macro locations on chips
The macro’s location affects the test pins’ location, again causing a problem insetting the direct-access mode.

7. Universal Test Interface
The memory cell array’s minimum unit is 1 Mbit. In this figure, the word line direction is horizontal and the bit line direction is vertical. To increase the DRAM macro’s capacity, we placed several copies of the 1-Mbit array in the vertical direction using the memory generator. We routed global bus lines over the memory cell array in the vertical direction.

8. Universal Test Interface implementation
The Universal Test Interface consists of 34 test pins. One bit is for test mode entry, and 5 bits are dedicated to command input for control of the DRAM macro. We use the next 18 bits for address and/or data inputs, and sometimes for subcommands for long word commands. The next 9 bits are for data outputs. The bit width of data I/O is usually 8 bits at the test interface. The ninth bit is used for parity-bit configuration. The last bit is for macro selection when two or more DRAM macros are embedded on the same chip.

9. Universal Test Interface implementation
The circuits comprising the Universal Test Interface decode the command and demultiplex the address, which is multiplexed at the test interface to reduce the number of test pins. The interface sends the decoded command and address to the control circuits through the test signal bus.

10. Multimacro testing
The interface provides 24 pins for test command, address, and data inputs for every macro. Nine bits of test data output from each macro are multiplexed at the logic portion. The macro select command is implemented in the test circuits. Only one macro, selected by the macro select command, operates at a time.

11. Self-Burn-in Mode
After test mode entry, the test command puts the DRAM macro into burn-in mode. In this mode, the DRAM operates according to the test pattern generated by the pattern generator. Only one clock pin is necessary to operate the pattern generator.

12. Using Universal Test Interface
“Reduce Test Cost”
Covers Various Products
Easy to Design
Easy to Handling
Mutimacro Testing
Self-Burn-In Mode
[ Multiplexing Test Pins ]
Necessary for Testing Setup/Hold Time

13. Thank You!