1. CSCI206 - Computer Organization & Programming
Direct Mapped Caches
zyBook: 12.3

2. Constructing the cache
The cache algorithm determines what data should be stored in the cache
Another question is where in the cache should the data be stored?
needs to be fast to check for hit/miss
The direct mapped cache is the simplest cache algorithm

3. Direct mapped (DM) cache
Each memory address is directly mapped to exactly one (and only one) location in the cache
Cache is smaller than main memory, so many addresses map to the same location in the cache
When memory is accessed it is stored in the cache, any prior data at that cache location is removed (overwritten)

4. Address
Value 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DM Cache Example
Suppose we have a 4-bit main memory address range (16 words) and a 2-bit cache memory address range (4 words)
Index
Value 1 2 3

5. DM Cache Access For example, access memory address 3
First compute index 3 % 4 = 3
Is the data at this index valid?
Is this data from address 3 or 7, 11, 15?
Need additional data in the cache
- valid (1-bit) set to 1 if data is valid
- tag, the upper portion of the
address bits
TAG
CACHE INDEX
MEMORY ADDRESS

6. DM Cache Access (address 7)
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Access (address 7)
index = 7 mod 4 = 3
tag = 7 >> 2 = 01
Index
Value
Valid
Tag 1 2 3 H 01
TAG
CACHE INDEX 01 11
MEMORY ADDRESS
0111

7. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 4 8 1 2 3 D
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 4 8
Index
Value
Valid
Tag 1 2 3 D 00

8. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 1 2
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8
Index
Value
Valid
Tag 1 2 3 D 00

9. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 1 F
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8
Index
Value
Valid
Tag 1 F 01 2 3 D 00

10. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 1 F
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8
Index
Value
Valid
Tag 1 F 01 2 3 D 00

11. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 A 1
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8
Index
Value
Valid
Tag A 1 01 F 2 3 D 00

12. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10 A
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
Index
Value
Valid
Tag A 1 01 F 2 3 D 00

13. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
Index
Value
Valid
Tag I 1 10 F 01 2 3 D 00
Tag in cache (01) doesn’t
match the address tag (10)

14. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10 I
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
Index
Value
Valid
Tag I 1 10 F 01 2 3 D 00

15. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
HIT
Index
Value
Valid
Tag I 1 10 F 01 2 3 D 00
Tag in address (00) match
that in cache (00)

16. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
HIT
Index
Value
Valid
Tag I 1 10 F 01 2 3 D 00

17. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
HIT
Index
Value
Valid
Tag E 1 01 F 2 3 D 00

18. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
HIT
Index
Value
Valid
Tag E 1 01 F 2 3 D 00

19. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
HIT
Index
Value
Valid
Tag I 1 10 F 01 2 3 D 00

20. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
HIT
Index
Value
Valid
Tag I 1 10 F 01 2 3 D 00

21. DM Cache Example ADDR CACHE INDEX TAG RESULT 3 00 MISS 5 1 01 4 8 10
Address
Value A 1 B 2 C 3 D 4 E 5 F 6 G 7 H 8 I 9 J 10 K 11 L 12 M 13 N 14 O 15 P
DM Cache Example
ADDR
CACHE INDEX
TAG
RESULT 3 00
MISS 5 1 01 4 8 10
HIT
Index
Value
Valid
Tag I 1 10 F 01 2 3 D 00
hit rate = 2/8

22. Designing a 4KB MIPS DM Cache
MIPS address space is 32-bit, word aligned
Cache indexes are also word aligned
lower two bits of address are the byte offset
4 KB cache has 1 K words (4 bytes / word)
1 K cache indexes = 10 bit index (2^10 = 1024)
MEMORY ADDRESS (32 BIT)
TAG
CACHE INDEX
BYTE OFFSET
20 BITS
10 BITS
2 BITS

23. 4 KB MIPS DM Cache

24. Exploiting Spatial Locality
Load extra words near other memory accesses into the cache
For example
lw $t0, 16($s0)
load 16($s0) through 32($s0) into the cache

25. Organize Cache into Blocks
Rather than caching words, cache blocks
block size is a power of 2 for easy indexing
On a miss, a whole block is cached
To exploit spatial locality
Example, 4 KB cache with 16 Byte blocks
MEMORY ADDRESS (32 BIT)
TAG
BLOCK INDEX
BLOCK OFFSET
BYTE OFFSET
20 BITS
8 BITS
2 BITS
16 bytes/block = 4 words/block
4 KB / 16 B/block = 256 blocks
need 2 bit block offset
and 8 bit block index

26. DM Cache Access
(block address)
(number of blocks)

27. Optimal Block Size
FIGURE 5.11 Miss rate versus block size. The miss rate goes up if the block size is too large relative to the cache size. Each line represents a cache of different size.

28. 16 KB MIPS DM cache w/ 64 B blocks
16 KB / 64 B = 256 cache indexes (lines)
8 bits for index
64 B / 4 B = 16 words per cache line
4 bits for block offset
2 bits for byte offset
Sometimes the block offset and byte offset are combined into a single offset field.
MEMORY ADDRESS (32 BIT)
TAG
CACHE INDEX
BLOCK OFFSET
BYTE OFFSET
18 BITS
8 BITS
4 BITS
2 BITS

29. 16 KB MIPS DM cache w/ 64 B blocks