1. Progress Report Algorithm Mapping onto Hardware in Simulink – IBOB/ROACH Environment
Yuta Toriyama
November 19, 2010

2. Project Goal
Goal: Hardware Implementation of Simplex Algorithm for use with Flash ADC optimization
Accompanies design of ADC for low-power bio-medical applications which could allow for non-uniform quantization
Need small devices and/or lower supply voltages
Problem: The relative process variability increases
IC design today is largely application driven. The applications enforce constraints which thereby influence our design methodologies. Example applications....

3. Flash ADC Yield
Yield: % that measures the proportion of ADCs with correct functionality. Decision levels from V0 to VN are monotonically increasing. 1 1 1 1

4. Flash ADC Yield Assume a Gaussian pdf: & Solid line – calculated yield
X – 10,000 pt. Monte Carlo

5. Probabilistic Approach
Problem:
Choose the active comparators
Turn off power to non- working comparators
Constraints:
Maximize SNR
Requirements:
Threshold values and indexes of chosen comparators must be monotonically increasing
Single 1 output to decoder 1 X 1 1 X
Logic
Encoder X X

6. Network Formulation of ADC1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1
= A
nodes
arcs

7. Cost Vector Formulation
Calculate the noise power contribution of each arc: Vj
Ck =
for all k = {1,2,Numarcs} Vi
di = 4
Allows for the inclusion of non-uniform distributions

8. LP Formulation maximize cTx s.t. Ax = [1 0 0 . . .-1]T 0 ≤ xi ≤ 1, i
Optimal solution satisfies xi  {0,1}
Arcs with xi=1 identify the path from V1 to VN that maximizes the SNR for a given input pdf 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1
= A
nodes
arcs

9. Simplex Algorithm
Simplex algorithm solves the LP very quickly even for large matrices
Main operation is series of Gaussian eliminations
Things to note:
initial matrix setup
finding an initial basic feasible solution 1 1 -1 1 1 1 1 1 1 1 1 1 -1 1 1

10. Hardware Implementation
Design Considerations
Speed requirements: low
Area/resource limitations
Memory Limitations:
IBOB has ~4Mb RAM on FPGA
ROACH has ~8Mb RAM on FPGA + 72Mb on board
Total Memory used (Kb): 3,240 out of 8, %
For example:
Storing the A matrix with sign bit + coordinates
(Makes Simplex implementation more difficult)

11. Hardware Implementation
Simplex Algorithm is very serial by nature
Possibility of tradeoff between:
Performance (ENOB) of Flash ADC
Complexity of implementation of optimization algorithm

12. Hardware Implementation

13. Testing Simulink simulation only allows ~k’s of clock cycles
Simplex algorithm takes millions of cycles to complete
Building and testing in small chunks:
Cannot test design as a whole
Many bugs in connecting small blocks
Putting design on FPGA and test using KATCP:
Painfully slow debug cycle
Signal visibility must be built into the Simulink design
Possible: Extract HDL and use Modelsim:
Need to close tool flow loop back to MATLAB
Signal visibility is better but still low
Design differs between HDL simulation & targeting FPGA

14. Testing Current Strategy: Build design & map to FPGA
Send input & Receive output thru MATLAB
IBOB – read/write_xps
Slow & somewhat unreliable link
Makes script testing difficult
ROACH - KATCP:
Much faster than read/write_xps & more reliable
I have written a simple tutorial, up on the wiki

15. Future Work
Hook it up with Vicki’s chip to see it in action (hopefully)
Simulink -> HDL -> Modelsim -> MATLAB toolflow:
Possible demand for it in the future, especially if IBOB/ROACH used for more algorithm mapping