1. ASU Summer Robotics Camp
VPL-Based Simulation
Dr. Yinong Chen

2. Table of Contents 1 Design Process with Simulation 2
Logic Design of an ALU 3
VPL Simulation of Gates 4
Testing 5
Robotics Simulation

3. Decide the Course of Action
Design Process with Simulation: For Visualizing the Design and for Pre-Evaluation of the Implementation 1
Define
Problem 2
Generate
Solutions 3
Decide the Course of Action
Simulation 4
Implement Solution 5
Evaluate
Solution

4. What is Simulation?
The process of imitating a real phenomenon with a set of mathematical formulas.
Simulation is often based on modeling: Creating mathematical models to imitating real thing.
Advanced computers and programs are the major driving force in creating useful simulations. They can simulate weather conditions, chemical reactions, atomic reactions, even biological processes.
In theory, any phenomena that can be reduced to mathematical data and equations can be simulated on a computer.
In practice, however, simulation is extremely difficult because most natural phenomena are subject to an almost infinite number of influences.
One of the challenges to developing useful simulations is to determine which are the most important factors

5. Logic Design: Analogue versus Digital

6. Elements of (Propositional) Logic
Proposition: A statement that can either be true or false:
One plus two is three
There is a Nobel prize winner from Arizona State University
The sky is blue
How old are you?
You must ride a bike to school!
Logic connectives
AND (), OR (), NOT (), IMPLIES ()
light is on  tank is full
(Light is off)  (bulb is not broken)  tank is empty
Truth and falsity values – Truth Table

7. Truth Table as a Specification
NOT
propositional variable statement
a ¬ a
false true
true false
AND
a b a  b
false false false
false true false
true false false
true true true
a a
0 1
a b ab
0 0 0
0 1 0
0 0
1 1 1

8. Truth Table (Contd.) OR a b a  b false false false false true true
true false true
true true true
a b ab
0 0 0
0 1 1
0 1
1 1 1

9. Building Blocks of a Computer
Basic Building Blocks
Truth Tables
a b ab
0 0 0
0 1 0
0 0
1 1 1
a b ab
0 0 0
0 1 1
0 1
1 1 1
a a
0 1
AND gate
c = ab a b c
OR gate
c = a  b
NOT gate
c = a
NAND gate
c = (ab) a b c
NOR gate
c = (a  b)
XOR gate
c = ab  ab
a b (ab) (ab) ab  ab

10. Design my Own Computer?
Yes, I can!

11. Five Modules of a Computer
CPU
Peripheral
Memory
Control
logic
input
ALU
output
Adder
Bus

12. Memory Design: bit and Byte
output 1
One bit can store a
“1” or a “0”
input
One-bit memory design
input
output
1-bit
8 bits = 1 Byte
Can store
a “character”
Or a short integer

13. The Entire Memory, with 32-bit address space and byte-addressable
2 1 0
Hex address h h h Ch h h h Ch h h h Ch h
FFFFFFF0h
FFFFFFF4h
FFFFFFF8h
FFFFFFFCh
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
The Entire Memory, with 32-bit address space and byte-addressable
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
. . .
. . .
. . .
. . .
. . .
1 byte
1 byte
1 byte
1 byte

14. Designing the Adder a 1 0 0 1 0 1 1 b + 1 0 1 0 1 1 carryIn+ a b
sum
carryOut a b
carryIn a b
carryIn .

15. Simulating a One-Bit Adder
Use a Computer Program in VPL to imitate the Design
Design
Testing

16. ALU Design: one-bit adder
CarryOut
Sum 1 b
CarryIn
input
output
carryIn a b
carryOut
sum

17. Simulation in VPL: NOT Gatec a

18. Simulation in VPL: OR Gateb c
Simulation in VPL: OR Gate

19. Simulation in VPL: AND Gate
first
second
output
Simulation in VPL: AND Gate

20. Simulation in VPL: XOR Gateb c
Simulation in VPL: XOR Gate

21. Define Before Using: Define the input whenever you see a warning sign
One-Bit Adder
carryIn a b
carryOut
sum
Define Before Using: Define the input whenever you see a warning sign

22. Testing the One-Bit Adder

23. One-Bit ALU

24. Define Before Using: Define the input whenever you see a warning sign

25. Testing the One-Bit ALU
op0
op1
op2
carryIn
first
second