Analog Design for the Digital World

Analog Design for the Digital World
Class 4: A/D and D/A November 20, 2014 Charles J. Lord, PE President, Consultant, Trainer Blue Ridge Advanced Design and Automation

This Week’s Agenda 11/17 Op Amps – Ideal, Reality, and Embedded 11/18 Resonant Circuits and Filters 11/19 Grounding and Shielding 11/20 A/D and D/A 11/21 Design and Test

“REAL WORLD” SAMPLED DATA SYSTEMS CONSIST OF ADCs and DACs
ADC SAMPLED AND QUANTIZED WAVEFORM The real world problem consists of taking a continuous signal (analog) and applying decisions by means of digital signal processing to the signal. DSP allows for efficient and cost effective means of allocating information (bandwidth, capacity) correctly. Consider a very basic digital transceiver design consisting of a receive path and a transmit path. In the Rx path a continuous analog signal that represents some element of information is captured at a finite point in time. This signal could be represented as a voltage swing over time. The conversion step occurs when that voltage swing is converted to a digital representation. The resulting digital representation, or codes, can be processed to extract the information content within that signal. Depending on the particular characteristic of that information, certain decisions are made such as route this piece of info to another network node or take a certain action with the receiver at a particular time. The transmit path is the exact opposite where the info needs to be ‘delivered’ to a real world device. DAC RECONSTRUCTED WAVEFORM

What is an Analog-Digital Converter?
INPUT DIGITAL OUTPUT RESOLUTION N BITS REFERENCE Analog Input DIGITAL OUTPUT CODE = x (2N - 1) Reference Input Produces a Digital Output Corresponding to the Value of the Signal Applied to Its Input Relative to a Reference Voltage Finite Number of Discrete Values : 2N Resulting in Quantization Uncertainty Changes Continuous Time Signal into Discrete Time Sampled Representation Sampling and Quantization Impose Fundamental yet Predictable Limitations An analog-to-digital converter produces a digital output which corresponds to the value of the analog input signal. The digital output value corresponds to the relative value of the analog input signal with respect to a fixed reference voltage and, in its most basic form, is determined by the relationship above. A key element of the transformation from the analog domain to the digital domain is that an analog variable of infinite resolution is now represented by finite discrete values. The analog input is quantized into 2N discrete levels, where N is the resolution of the converter. This results in a quantization error or uncertainity from the A/D conversion process. The quantization and sampling of the input signal thus impose fundamental limitations on the A/D conversion process. However, these limitations are predictable. Let’s look first at the quantization process. The A/D conversion process also changes a continuous analog signal in the time domain to a digital signal which is represented by values which occur at discrete intervals. The continuous analog signal is sampled and converted to a digital word at these discrete time intervals.

Sampling Process Representing a continuous time domain signal at discrete and uniform time intervals Determines maximum bandwidth of sampled (ADC) or reconstructed (DAC) signal (Nyquist Criteria) Frequency Domain- “Aliasing” for an ADC and “Images” for a DAC The sampling process is the representation of a continuous time domain signal at discrete and uniform time intervals. The maximum amount of information content, or bandwidth, is determined by the Nyquist sampling theory which states that the maximum bandwidth of a data conversion process is equal to ½ the applied sampling. Also the sampling rate has an affect on where signal aliasing occurs in the frequency domain. In general, for a given bandwidth the higher the sampling rate, the less stringent the filtering needs to be.

Quantization Process Quantization Process
Representing an analog signal having infinite resolution with a digital word having finite resolution Determines Maximum Achievable Dynamic Range Results in Quantization Error/Noise The quantization process is the representation of the magnitude, in code form, of the continuous analog signal. The number of bits in the quantization process determines the number of discrete levels and, therefore, it determines the smallest resolvable signal. Note, in the diagram above, an analog input in the range shown gives the same digital code. The ratio of this smallest resolvable signal or least significant bit (LSB) to the largest resovable signal (fullscale) defines the maximum achievable dynamic range. Any Analog Input in this Range Gives the Same Digital Output Code

Conversion Relationship for an Ideal A/D Converter
DIGITAL OUTPUT 1 LSB ANALOG INPUT 1/ /8 3/ / / / /8 001 010 011 100 101 110 111 This shows the conversion relationship for an ideal 3-bit converter. The smallest resolvable signal is 1 LSB which is equal to FS/23 or FS/8. The digital output has 8 discrete values representing a linear transfer function.

Quantization Noise 001 010 011 100 101 110 111 1/8 2/8 3/8 4/8 5/8 6/8
7/8 FS NORMALIZED ANALOG INPUT DIGITAL OUTPUT quantization noise error We have previously talked about quantization errors and how they determine dynamic range etc. This plots shows the profile of the quantization error as it tracks a ramped analog input voltage. At the centre of each of the codes, the quantization error is 0. As the input voltage increases but the digital code remains constant, the quantization error goes negative. At the next code transition, the digital output now jumps ahead of the analog input voltage ramp and quantization error jumps positive. The profile is repeated at each code of the ADC transfer function. q = 1 LSB

Quantization Noise (con’t)
0 volts +q/2 -q/2 The RMS value of the quantization noise sawtooth is its peak value, q¸2, divided by Ö 3, or q ¸ Ö12 For Sine Wave Full Scale RMS Value is 2(N-1)/Ö2 For Saw Tooth Quantization Error Signal RMS Value is q /Ö12 Thus S/N is x 2N Expressed in dB as N, where N is the resolution of the A/D converter Read through Bullets

ADC Resolution vs. Quantization Parameters
This table shows the relationship between the analog input range, or full scale, and the LSB size for different resolutions. The full scale in this case is 2.5V, and a selection of ADCs are quoted as examples.

Analog Input Signal Definitions
There are various different types of analog inputs and this slide explains the differences between them. The first diagram shows a Unipolar, Single Ended analog input signal. The analog input is applied to the VIN pin of the ADC, has an amplitude of the Full scale input voltage (FS) and spans from 0V to +FS. The second diagram shows a Unipolar, Fully Differential analog input signal. In this case, the ADC has a positive and a negative analog input, VIN+ and VIN-. These inputs are driven by two equal signals which span from 0 V to +FS, that are 180° out of phase. The third diagram shows a Bipolar, Single Ended analog input signal. The analog input is applied to the VIN pin of the ADC, has an amplitude of ±FS/2 and is centered on ground. The fourth diagram shows a Bipolar, Fully Differential analog input signal. In this case, the ADC has a positive and a negative analog input, VIN+ and VIN-. These inputs are driven by two equal signals of amplitude ±FS/2, that are 180° out of phase. The two inputs are centered on ground. The fifth diagram shows a Pseudo Differential analog input signal. In this case, the ADC has a positive and a negative analog input, VIN+ and VIN-. The positive input is driven by a signal of amplitude FS, and the negative input is driven by a small DC voltage to provide an offset from ground or a ‘pseudo ground’ for the VIN+ signal.

DC Specifications (Ideal)
Ideal ADC code transitions are exactly 1 LSB apart. For an N-bit ADC, there are 2N codes. (1 LSB = FS/ 2N ) For this 3-bit ADC, 1 LSB = (1V/23 = 1/8th) Each “step” is centered on an eighth of full scale This slide shows an ideal transfer function for a 3-bit converter.

DC Specifications (DNL)
Differential Non-Linearity (DNL) is the deviation of an actual code width from the ideal 1 LSB code width Results in narrow or wider code widths than ideal and can result in missing codes Results in additive noise/spurs beyond the effects of quantization The ideal width for each code is 1LSB but in practice each code width is different from its neighbours. A DNL error is defined as the difference between the ideal 1 LSB step and the actual (real) step as one moves along the transfer function (DNL = actual - ideal). Thus, in the plot shown above, we are measuring the actual width of each code. For example a code with a width of 1.5 lsb would have a DNL of = 0.5 lsb. A missing code would have a width of zero and would have a DNL of = -1.0 lsb. DNL can never be less than -1.0, but has no upper limit. The effect of DNL error is to add “noise/spurs” to an ideal transfer function. This reduces the accuracy of the conversion beyond the limitations of quantization.

DC Specifications (INL)
Integral Non-Linearity (INL) is the deviation of an actual code transition point from its ideal position on a straight line drawn between the end points of the transfer function. INL is calculated after offset and gain errors are removed Results in additive harmonics and spurs INL error is not a measure of code width. It is a measure of the error in a code’s transition point. Ideally, the transition points should occur at exactly the 1/8th, 1/4th, etc voltages. Errors in the converter cause the actual code transitions to deviate from ideal. INL is usually measured with respect to code centres and is the worst deviation of any code centre from an ideal straight line drawn between the endpoints of the transfer function. This ideal straight line is calculated after both offset and gain errors are removed. Thus, in the plot shown above, we are measuring the deviation of its actual transition point from its ‘ideal’ transistion point after gain and offset are removed. Just like DNL, INL results in a reduction in accuracy of the converter. However, unlike DNL, INL errors can result in added harmonic components. (This will be demonstrated on the next slide.)

QUANTIFYING ADC DYNAMIC (AC) PERFORMANCE
Harmonic Distortion Worst Harmonic Total Harmonic Distortion (THD) Total Harmonic Distortion Plus Noise (THD + N) Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Analog Bandwidth (Full-Power, Small-Signal) Spurious Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Noise Power Ratio (NPR) or Multitone Power Ratio (MPR) There are two types of performance specification groups that are important in selecting the appropriate ADC. These two groups can be viewed as dynamic and static in nature. Although not completely independent of each other, they can tell you a lot about how the converter operates under certain conditions as well as the ‘quality’ of the ADC design. In the previous slides, we have talked about static performance of A/D converters. Now lets talk about some of the many dynamic performance parameters over the next few slides.

Fast Fourier Transform converts
time amplitude this… f1 2f1 3f1 ...to this frequency amplitude f1 2f1 3f1 A fast Fourier Transform converters an analog time domain signal to a frequency representation in the digital domain as shown above

Nyquist Bandwidth & Aliasing
2 Signals that are Mixed Together Produce Sum and Difference Frequency Components Nyquist Theory Stipulates that the Signal Frequency, FSIGNAL must be < to ½ FSAMPLING to Prevent a Condition Known As “Aliasing”, in which the Difference Component Appears Within the Signal Bandwidth of Interest Read Through Bullets

The Nyquist Bandwidth & Aliasing (FSIGNAL < ½ FSAMPLING)
1 MHz 4 MHz fsampling fsampling + fsignal fsampling - fsignal signal passband 3 MHz 5 MHz fsignal The Signal Frequency Is < 1/2 the Sampling Frequency and so the Sum and Difference Components Fall Outside (Beyond) the Signal Passband The Signal Frequency Is < 1/2 the Sampling Frequency and So the Sum and Difference Components Fall Outside (Beyond) the Signal Passband

The Nyquist Bandwidth & Aliasing (FSIGNAL > ½ FSAMPLING)
fsampling- fsignal fsignal fsampling fsampling + fsignal 2.5 MHz 1.5 MHz 1 MHz “Alias” 0.5 MHz The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An “Alias” or False Image is Thus Created that Falls Within the Passband of Interest. There are specific applications where the input signal is bandlimited whereby the A/D converter can actually resolve input frequencies which are beyond the Nyquist frequency. These applications are known as undersampling applications. The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An “Alias” or False Image is Thus Created that Falls Within the Passband of Interest.

SINAD, ENOB, and SNR SINAD (Signal-to-Noise-and-Distortion Ratio)
The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, including harmonics, but excluding dc ENOB (Effective Number of Bits) SNR (Signal-to-Noise Ratio, or Signal-to-Noise Ratio Without Harmonics) The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, excluding the first five harmonics and dc One of the basic ADC figures of merit is its ability to convert the signal of interest and keep it separate from other noise elements within the signal chain. It’s best defined as the ratio of the rms signal amplitude to the mean value of the root sum squares of all the spectral components. SINAD is this ratio that includes all harmonics. SNR is this ratio but it excludes the first 5 harmonics. ENOB or effective number of bits is another figure of merit and can be derived from SINAD. It is interesting to note that SNR does depend on signal input level. In an ideal converter, the higher the input level, the higher the SNR. Unfortunately, in the real world the ADC has a maximum input level. Take this plus the fact that it is not an ideal converter, there is a slightly different curve. (solid line vs the dotted line) ====================================== Clipping …in the ADC defines the SNRmax (full scale range) Delta between are based on the errors introduced in the Rx signal chain…. A perfect converter, quant error exists… other errors intro’d into signal chain (and others within the ADC)… increase this delta.

Successive Approximation ADC
“Recursive” One-Bit Sub-Ranging Architecture The successive approximation ADC is one of the simplest architectures used and it is the “work horse” of A/D converters. It is by far the most common type of converter used due to its precision and low-cost. AS can be seen, there are only three blocks in the main loop, a DAC, a comparator, and an SAR register. The way is works is on each clock cycle, the SAR register “tests” one bit at a time, starting with the MSB. For example, it sets the MSB high and all other bits to zero. The DAC then outputs the analog equivalent, (which is mid-scale). The comparator measures whether the analog input is below or above the DAC voltage. If the output of the DAC is less than the VIN voltage, then the output of the comparator will be high and the MSB is kept at a one; if the output of the DAC is greater than the VIN voltage, then the output of the comparator will be low and the MSB is reset to zero. This information to the SAR register and this value is maintained for the MSB of the DAC for the rest of the routine. On the next clock cycle, the 2nd MSB is set to one. The DAC output will now either be 1/4 or 3/4 or full scale depending on the MSB. It does this repeatedly until all bits are resolved. Note: this ADC architecture requires a held dc voltage as its input, which is the reason for the SHA. As you can imagine, this type of architecture is very efficient in terms of power and size. The main disadvantage is that the sample rate is dependent on the resolution.

How a Successive Approximation A/D Converter Works
Rising/Falling Edge of Convert Start Pulse Resets Logic Falling/Rising Edge Begins Conversion Process Bit Comparisons Made on Each Clock Edge Conversion Time Equals Number of Comparisons (Resolution) Times Clock Period The Accuracy of Conversion Depends on the DAC Linearity and Comparator Noise Read Through Bullets

How Successive Approximation Works
EXAMPLE : ANALOG INPUT = 6.428V, REFERENCE = V MSB 5.000V 2SB 2.500V 3SB 1.250V LSB 0.625V VIN > 5.000V VIN > 6.875V VIN > 6.250V VIN > 7.500V YES 1 NO This example works through a 4-bit successive approximation routine for an input of 6.428V for an A/D converter with a 10V fullscale. When the MSB of the D/A converter is turned on, the output of the D/A converter is 5V. This is lower than the VIN voltage and, therefore, the bit is retained as a 1. The next bit is then turned on, resulting in a D/A converter output of 7.5V. This is greater than the VIN voltage so this bit is rejected and returned to a 0. The third MSB is then tried, with a resulting output voltage of 6.25V from the D/A converter. This is less than the VIN voltage so this bit is retained as a 1. Finally, the LSB of the D/A converter is turned on to give an output voltgae of 6.875V. This makes the D/A output voltage greater than Vin and the LSB is rejected and returned to a 0. The successive approximation routine is now complete with a resultant digital word of 1010 in the SAR register, representing the digital output word from the SAR ADC.

Advantages to SAR A/D converters Low Power (12-bit/1.5 MSPS ADC: 1.7 mW) Higher resolutions (16-bit/1 MSPS) Small Die Area and Low Cost No pipeline delay Tradeoffs to SAR A/D converters Lower sampling rates Typical Applications Instrumentation Industrial control Data acquisition This example works through a 4-bit successive approximation routine for an input of 6.428V for an A/D converter with a 10V fullscale. When the MSB of the D/A converter is turned on, the output of the D/A converter is 5V. This is lower than the VIN voltage and, therefore, the bit is retained as a 1. The next bit is then turned on, resulting in a D/A converter output of 7.5V. This is greater than the VIN voltage so this bit is rejected and returned to a 0. The third MSB is then tried, with a resulting output voltage of 6.25V from the D/A converter. This is less than the VIN voltage so this bit is retained as a 1. Finally, the LSB of the D/A converter is turned on to give an output voltgae of 6.875V. This makes the D/A output voltage greater than Vin and the LSB is rejected and returned to a 0. The successive approximation routine is now complete with a resultant digital word of 1010 in the SAR register, representing the digital output word from the SAR ADC.

Flash or Parallel ADC 2N-1 comparators form the digitizer array, where N is the ADC resolution Analog input is applied to one side of the comparator array, a 1 lsb reference ladder voltage is applied to the other inputs. The comparator array is clocked simultaneously and decides in parallel. Output logic converts from thermometer code to binary The flash ADC architecture is probably the faster ADC architecture available. The reason for this is its parallel but shallow configuration. The way it works is by first setting up reference voltages. This is usually done with a series connected resistor ladder. These reference voltage are what will correspond to code transition points in the ADC. In this case, the reference voltages are: 1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16. Notice that for M possible output codes, there are only M-1 reference points (and comparators). The reason for this is the first reference voltage defines two states (above and below), while each additional one only adds one additional state (middle). Once the references are set, an analog voltage can be applied. Depending one what the analog voltage is, some comparators will be high and some will be low. The transition point correponds to what the output code will be. For example, if the analog input is at 1/2 scale, the bottom four comparators will be high and the top three will be low. The encoder logic recognizes this and will then output 100. One interesting note, is that this architecture does not require a held dc input. This is because the comparators are always running and their output data can be latched in a single instance in time. However, in some instances when fast moving analog inputs are being digitized, a track and hold circuit can help improve performance and reduce “sparkle” codes.

Flash or Parallel ADC Advantages to Flash A/D converters
Fastest conversion times (up to 1 GSPS) Low data latency Tradeoffs to Flash A/D converters Higher power consumption High capacitive input is difficult to drive Typical Applications Video digitization High-speed data acquisition The flash ADC architecture is probably the faster ADC architecture available. The reason for this is its parallel but shallow configuration. The way it works is by first setting up reference voltages. This is usually done with a series connected resistor ladder. These reference voltage are what will correspond to code transition points in the ADC. In this case, the reference voltages are: 1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16. Notice that for M possible output codes, there are only M-1 reference points (and comparators). The reason for this is the first reference voltage defines two states (above and below), while each additional one only adds one additional state (middle). Once the references are set, an analog voltage can be applied. Depending one what the analog voltage is, some comparators will be high and some will be low. The transition point correponds to what the output code will be. For example, if the analog input is at 1/2 scale, the bottom four comparators will be high and the top three will be low. The encoder logic recognizes this and will then output 100. One interesting note, is that this architecture does not require a held dc input. This is because the comparators are always running and their output data can be latched in a single instance in time. However, in some instances when fast moving analog inputs are being digitized, a track and hold circuit can help improve performance and reduce “sparkle” codes.

FIRST-ORDER SIGMA-DELTA ADC
CLOCK Kfs fs INTEGRATOR VIN ò DIGITAL FILTER AND DECIMATOR å A + N-BITS + _ _ fs LATCHED COMPARATOR (1-BIT ADC) B +VREF 1-BIT, Kfs 1-BIT DATA STREAM 1-BIT DAC –VREF SIGMA-DELTA MODULATOR

SIGMA-DELTA ADCs Advantages to Sigma-Delta A/D converters
High resolutions and accuracy (24-bits) Excellent DNL and INL performance Noise shaping capability Tradeoffs in Sigma-Delta A/D converters Limited input bandwidth Slower sampling rates Typical Applications Precision data acquisition and measurement Medical instrumentation

What is a Digital-Analog Converter?
RESOLUTION = N BITS REFERENCE INPUT ANALOG OUTPUT DIGITAL INPUT Digital Input Analog Output = x Reference Input (2N - 1) Produces a Quantized (Discrete Step) Analog Output (Voltage or Current) in Response to Binary Digital Input Code Digital Inputs May Be TTL, ECL, CMOS, LVDS… A reference quantity (either voltage or current) is accurately divided into binary and/or linear segments. The digital input drives switches that connect an appropriate number of segments to the output. Finite Number of Discrete Values : 2N Resulting in Quantization Uncertainty Sampling and Quantization Impose Fundamental yet Predictable Limitations A digital-to-analog converter produces an analog output which corresponds to the value of the digital input signal. The analog output value corresponds to the relative value of the digital input signal with respect to a fixed reference value and, in its most basic form, is determined by the relationship above. A key element of the transformation from the digital domain to the analog domain is that a series of finite discrete values is now represented by an analog variable.

Sampling Process Representing a continuous time domain signal at discrete and uniform time intervals Determines maximum bandwidth of sampled (ADC) or reconstructed (DAC) signal (Nyquist Criteria) Frequency Domain- “Aliasing” for an ADC and “Images” for a DAC The sampling process is the representation of a continuous time domain signal at discrete and uniform time intervals. The maximum amount of information content, or bandwidth, is determined by the Nyquist sampling theory which states that the maximum bandwidth of a data conversion process is equal to ½ the applied sampling. Also the sampling rate has an affect on where signal aliasing occurs in the frequency domain. In general, for a given bandwidth the higher the sampling rate, the less stringent the filtering needs to be.

Quantization Process Quantization Process
Representing an analog signal having infinite resolution with a digital word having finite resolution and an analog output which only exists in discrete levels Determines Maximum Achievable Dynamic Range Results in Quantization Error/Noise The quantization process is the representation of the magnitude, in code form, of the continuous analog signal. The number of bits in the quantization process determines the number of discrete levels and, therefore, it determines the smallest resolvable signal. Note, in the diagram above, an analog output in the range can only exist at the discrete levels shown. The ratio of this smallest signal level or least significant bit (LSB) to the largest reproducable signal (fullscale) defines the maximum achievable dynamic range.

Conversion Relationship for an Ideal D/A Converter
DIGITAL INPUT 1/8 1 LSB ANALOG OUTPUT 2/8 3/8 4/8 5/8 6/8 7/8 This shows the conversion relationship for an ideal 3-bit converter. The smallest resolvable signal is 1 LSB which is equal to FS/23 or FS/8. The digital output has 8 discrete values representing a linear transfer function.

DAC Resolution, LSBs and More...
This table shows the relationship between the analog output range, or full scale, and the LSB size for different resolutions. The full scale in this case is 10V.

DC Specifications (DNL & Montonicity)
Differential Non-Linearity (DNL) is the deviation of an actual step size from the ideal 1 LSB step. DNL error results in smaller or larger step sizes than ideal DNL error esults in additive noise/spurs beyond the effects of quantization A DAC Is Monotonic If Its Output Increases or Remains the Same for an Increment in the Digital Code Conversely, a DAC Is Non-Monotonic If the Output Decreases for an Increment in the Digital Code The ideal step size for each code is 1LSB but in practice each step size is different from its neighbours. A DNL error is defined as the difference between the ideal 1 LSB step and the actual (real) step as one moves along the transfer function (DNL = actual - ideal). Steps sizes are larger or smaller than ideal due to DNL errors. From a dynamic performance perspective, the effect of DNL error is to add “noise/spurs” to an ideal transfer function. This reduces the accuracy of the conversion beyond the limitations of quantization. A key requirement for a DAC is that it is monotonic, that is, its analog output voltage should increase or remain the same as the DAC’s digital code increases. If the output of the DAC decreases as the digital code increases, the DAC is said to be non-monotonic.

Correlation Between DC and AC Performance
DNL can be closely correlated to SFDR for low frequencies below the “knee” Dynamic errors include: Nonlinear output impedance Digital Feedthrough Signal-dependant glitching or settling A typical plot of SFDR vs. output frequency has a characteristic as shown in the plot, with a flat region at “low” frequencies dropping off at higher frequencies. Low frequency performance is dominated by the static linearity characteristics. At a certain point the dynamic errors dominate and the SFDR is reduced as the output frequency increases. A major focus for new DAC designs is to extend the “knee” frequency at which the static and dynamic errors have equal contributions.

Settling Issues Static Errors (INL, DNL) occur after transition, resulting in low-frequency distortion Dynamic Errors happen during transition and are typically proportional to step size (i.e. worse for high frequencies and/or large amplitudes) This plot shows the ideal zero-order hold step response of the DAC output (dashed line) and a more typical output that demonstrates some of the errors that can be observed. DAC errors can be broken into two categories: static and dynamic. Static errors are observed after the output has settled to a new value, and are typically caused by element mismatches that result in non-ideal linearity characteristics or gain errors. Low-frequency SFDR performance can be closely correlated to dc linearity performance, and can also impact small signal SFDR at higher frequencies. Dynamic errors occur during a code transition and are usually dependant on the step size. These errors typically dominate at higher output frequencies.

A Simple D-A Converter Using a Kelvin Divider
VREF R1 R2 R3 R4 RN + - VOUT Not a Practical Approach Output is Monotonic For N Bit Resolution, 2N Resistors (Taps) are Required The DACs most commonly used as examples of simple DAC structures are binary weighted DACs or ladder networks. The simplest structure of all is the Kelvin divider or String DAC. An N-bit version of this DAC simply consists of 2N equal resistors in series and 2N switches, one between each node of the chain and the output. The output is taken from the appropriate tap by closing just one of the switches. The output of a DAC for an all 1s code is 1 LSB below the reference, so a string DAC intended for use as a general purpose DAC has a resistor between the reference terminal and the first switch. This is also the architecture used in digital potentiometers. In an ideal potentiometer, all 0s and all 1s codes should connect the variable tap to one or other end of the string of resistors. So a digital potentiometer, while basically the same as a general purpose string DAC, has one fewer resistor and neither end of the string has any other internal connection.

Voltage Segment DAC x1 VREF R1 R2 VOUT R3 R4 RN
This diagram shows a segmented string DAC architecture. This architecture is sometimes called a Kelvin-Varley Divider. This architecture requires two chains of resistors, 2N resistors. It is obvious that by connecting a second string of resistors across adjacent taps on the first string we may further sub-divide the voltage between the two taps and thus increase resolution. This is one architecture used in achieving monotonic behaviour at high (16-bit) resolutions Since there are buffers between the first and second stages the second DAC string does not load the first and the resistors in this string do not need to have the same value as the resistors in the other one. Cascaded string DACs are themselves intrinsically monotonic. Monotonicity is a key specification for all closed loop control applications. Having to buffer the main and sub-string has the potential to introduce linearity errors due to the buffer amplifiers and also introduce an area and power penalty into this architecture.

STRING DAC Architecture
Traditional String DAC requires 2n Resistors. Main DAC and Sub-DAC leads to 2N/2 + (2N/2 -1) Resistors Vsubdac=Rll(3R)=3R/4. VREF=1 Rtotal=R/4+(3R)/4+3R = 4R LSB = Vsubdac/3=R/4 Size, Power, and Cost Reduction. Resistor Matching Excellent- DPDM, no Trimming. Guaranteed Monotonic Voltage Output This is the newest string DAC architecture and it overcomes the shortcommings of previous string DAC architectures that required the sub string to be either buffered or be of a much higher impedance to overcome the loading affects of the sub-string on the main-string. With this new architecture the loading of the sub-dac is not treated as an error but is built into the overall DAC transfer function. It is intrinsically monotonic by design. Here the resistors in the two strings must be equal except for the the top resistor in the MSB string which is used to reduce gain error effects. The main-string consists of (2N/2) resistors and the sub-dac consists of (2N/2 -1) resistors. Because there are no buffers the sub-dac appears in parallel with the resistor in the main-string that it is switched across and loads it. This drops the voltage across that main-string resistor by 1 LSB of the sub-DAC – which is exactly what is required. Loading step =1 LSB, With Vref=1 and Ron=0 the ratio of the main string Resistor to sub dac resistor is 1:1. To account for non ideal switches subdac R is made slightly larger than the main DAC R. R/4 resistor is used to reduce gain error. This architecture allows the manufacture of guaranteed monotonic, high resolution, low power DACs in space saving surface mount packages.

A Simple Binary-Weighted D-A Converter
+ - 4R 2R S1 S3 S2 V RF I VOUT= -IRF A simple DAC can be easily implemented using a binary weighted network as shown. The current, I, is the sum of the individual currents through the input resistors. An n-bit DAC of this nature can be implemented with “n” resistors. The drawback to such a system is that a range of different resistance values are required, 2(n-1). The resistor ratios need to be tightly controlled to maintain accurate performance and maintain monotonic behaviour. This is very difficult to achieve in a production environment. A Simple Binary-Weighted Network. The Current I is the Sum of the Individual Currents Through R, 2R and 4R.

R-2R Ladder Network R and 2R Values Easy to Trim in Production
Match to 1 Part in 2n Will Yield n Monotonicity Absolute Value Not Important (typ kW, +/-20%) Voltage vs. Current Switching Mode The most common DAC structure is the R-2R ladder. It uses resistors of only two different values: their ratio is 2:1. An N‑bit DAC requires 2N resistors and they are quite easily trimmed in production. Absolute accuracy is not a key requirement and resistors can have a 20% tolerance but to yield a monotonic DAC the resistors need to match to 1 part in 2N. There are two ways in which the R:2R ladder network may be used as a DAC, known respectively as the current mode and voltage mode.

Current Steering Mode Current Steering Mode Constant Input Impedance
Output Impedance Varies with Code Vout = -D X Vref REF Bandwidths < 1 MHz Nonlinearity Increases with Decreasing Reference In a current steering DAC, the R2R ladder divides the input current into binary weighted currents and these currents are steered to Iout1 or Iout2 by current steering switches. Switches on-resistance is low enough to be negligible compared with the the R2R ladder resistors. Switch sizes are generally scaled so as not to affect the linearity performance of the DAC by ensuring each switch has the same voltage drop across it. The DAC termination resistor is generally tied to the IOUT 2 line to facilitate the biasing of this node for use in true single supply applications. Characteristics of this structure include: Fixed input impedance. DAC exhibits a code dependant output Impedance which varies from R to 3R. Output variation is not linear with code. Low offset amplifiers required to maintain linearity. Noise gain varies with DAC code due to variations in the output impedance. Noise gain is the gain seen by the input referred noise and error parameters and results in DNL errors. This architecture is the basis for the multiplying DAC. 62 64

Segmented R-2R 3, 4 or 5 Fully Decoded MSBs followed by R2R Ladder for LSBs Less Trimming in Production for Higher Resolution DACs Linearity Specs more readily achievable Lower Input Impedance - Less Distortion. Fixed Input Impedance. In an R2R ladder it is necessary to have very tight matching between each bit and the sum of the lesser bits in order to maintain monotonic behaviour. In a segmented design, these requirements are relaxed, making high resolution monotonic converters more practical. The most significant bits are decoded to select one of the segments. In the case of 3 bits of segmentation, 7/8 of the current flows in the parallel ladder structure and 1/8 in the R/2R structure. If this were a 14 bit DAC with 3 bits of segmentation then the R2R structure is basically an 11 bit DAC and this sets the accuracy of trim required to achieve performance. Therefore segmentation allows linearity specifications to be more easily achievable. The input impedance is much lower which means lower distortion. The architecture exhibits a fixed input impedance and an output impedance that varies with code as previously mentioned. 59 61

“Multiplying” DAC VREF V or I DIGITAL OUTPUT R-2R INPUT
In the current steering mode, the CMOS DAC multiplies the digital input value by the analog input voltage at the VREF pin. The input reference to the R-2R DAC can be AC or DC positive or negative. Reference bandwidths are generally less than 1MHz on older designs but bandwidths in excess of 10MHz can now be realized on fine line CMOS processes. Any applications requiring precision multiplication with minimal zero offset and very low distortion must consider the CMOS R-2R DAC as a candidate. Decreasing the amplitude of the reference input signal increases the nonlinearity.

Voltage Switching Mode
Output Voltage is Same Polarity as Input Constant Output Impedance Input Impedance Varies With Code VREF Limited to Volts Allows Single Supply Operation Connecting the R2R structure in the manner outlined above is known as voltage switching mode of operation. In this mode of operation the output is a voltage and not a current. A positive reference gives a positive output voltage and this allows for single supply operation. The DAC input impedance varies with code and the DAC output impedance is fixed. The voltage source connected to Vref should have a low dynamic impedance since it must drive a switched load. Vin is limited to low voltages because the switches in the DAC no longer see the same drain source voltages and thus exhibit differing on resistance. Since both IOUT1 and IOUT 2 are driven from low impedance sources glitch impulse is reduced. Higher reference voltages will degrade linearity due to reduced drive available for the CMOS switches. (Gate is driven to the positve supply and the source is tied to the reference input). Vin must always be positive so as to avoid forward biasing input protection diodes. 61 63

CMOS R-2R DAC Equivalent Circuit
+ - DVREF R RS CO VREF RFB CFB DAC This diagram shows the equivalent circuit for a CMOS DAC. A CMOS R-2R DAC is effectively modelled by its input impedance R, its output impedance Rs in parallel with its output capacitance Co, an output current related to the reference and the digital code loaded to the DAC. RFB is the feedback resistor used in conjunction with the output amplifier in converting the output current to a voltage. Cf is an externally applied capacitor connected in parallel with the feedback resistor to reduce ringing and prevent instability in the output.

CMOS Switched Current DAC
Scaling issues are simplified, no need for R-2R Allows Integration of Digital Signal Processing Good Device Matching for 12-bit linearity, calibration required for higher resolution Popular in Communications applications Current Sources are binarily weighted Because of the drawbacks in the bipolar implementation, CMOS has become favored for high-speed signal synthesis applications. The current sources are implemented as unit elements, with several of the most significant bits (MSBs) generated by combining binary sums of the unit elements. For example, in an 8-bit DAC the MSB would consist of 128 unit elements, while the next bit would be derived from 64 unit elements, and so on. In practice, the top 5 to 7 MSBs are created in this fashion, with the remaining lower bits being binary divisions of the lowest segment. Scaling is less of a problem, and on-chip calibration can be added with a minimal power and area hit to achieve resolution > 14 bits. With careful control of switching characteristics, excellent dynamic performance can be achieved. In addition, digital signal processing (DSP) functions can be integrated with the DAC to provide complete systems solutions. For these reasons this architecture has become popular for communications applications.

Terminating a Current Output DAC
Best AC performance Best DC Performance VCC VCOMP RFB IOUT IOUT - + + In most signal synthesis applications, the current output needs to be converted to a voltage to be amplified or upconverted. There are two basic ways to accomplish this. The first method is to connect the output to a resistive load. This will result in the best ac performance since an active element is not used, which would contribute some amount of noise and distortion. The load must be sized such that the resultant voltage does not exceed the compliance voltage of the DAC output, but typically needs to be backed off to achieve optimal performance. This configuration will not exhibit the best dc performance, because the output impedance drops as the voltage increases, which in turn degrades the linearity. For the best linearity performance, the output should be terminated into a virtual ground so the output voltage and the output impedance remain constant. The most common way to achieve this is to use a simple I-V converter as shown in the diagram on the right. The downside of this configuration is that most op-amps will not exhibit good distortion performance above a few hundred kilohertz. RLOAD VOUT - Compliance Voltage Virtual Ground

DAC Architecture Pros and Cons
Summary: Resistor String Inherent Monotonicity Compact Design Leading to the basis of Multi-Channel DACs Difficult to get High performance INL R-2R Ladder Good DC performance Suffer from distributed R-C effects and signal-dependant loading in frequency-domain applications Multiplying Capability Can Operate in Voltage Mode for Single Supply Applications Read Bullets

DAC Architecture Pros and Cons
Summary (con’t): Bipolar Switched Current Suffers AC limitations because R-2R is typically required to create LSB currents CMOS Switched Current Best Choice for frequency-domain applications: No R-2R to limit AC performance Good matching for DC specifications (calibration sometimes needed) Allows for integration with discrete signal processing blocks to ease implementation and improve performance Read Bullets

This Week’s Agenda 11/17 Op Amps – Ideal, Reality, and Embedded 11/18 Resonant Circuits and Filters 11/19 Grounding and Shielding 11/20 A/D and D/A 11/21 Design and Test

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Analog Design for the Digital World

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