1. Computer Architecture
CS423: Lecture 12
Dynamic Scheduling
Jahangir Ikram

2. COMPARISON
FP PIPELINE VS SCOREBOARD

3. Revision

4. Multiple Cycle Floating Point PipelineEX
Mem WB IF ID A 1 2 3 4 M .. 7
Divide
Function Unit
Latency
Initiation
/Re-Issue Interval
Integer ALU 1
Load/Store
FP Add 3
FP/Int Multiply 6
FP/Int Divide 24 25

6. Scoreboard of CDC 6600 Read Operands EX Mem Read Operands EX WB ISSUE
Register File
Scoreboard of CDC 6600
Read Operands EX
Mem
Read Operands EX WB
ISSUE
Read Operands A 1 A 2 A 3 A 4
Register File
Read Operands M 1 M 2 .. M 7
Read Operands
Divide
Check for WAW, FU
Check for RAW, Read Values from Register File when free
Check for WAR

7. IS RO EX WR Ask students to fill this and compare with 2 slides before
L.D F0,0(R2)
L.D F4,0(R3)
MUL.D F0,F0,F4
ADD.D F2,F0,F2
DADDUI R3,R3,8
DAADUI R3,R3,8
DSUBU R5,R4,R2
BNEZ R5, Loop

8. IS RO EX WR L.D F0,0(R2) L.D F4,0(R3) MUL.D F0,F0,F4 ADD.D F2,F0,F2
DADDUI R3,R3,8
DAADUI R3,R3,8
DSUBU R5,R4,R2
BNEZ R5, Loop

9. Data Hazards RAW Hazard WAW Hazard WAR Hazard ADD.D F3, F1, F2
SUB.D F5, F6, F3
WAW Hazard
DIV.D F3, F1, F2
SUB.D F3, F6, F5
WAR Hazard
DIV.D F3, F1, F2
SUB.D F5, F6, F3
ADD.D F3, F6, F7

10. TRUE and False Dependencies
Find Dependencies in this code
DIV.D F0,F2,F4
ADD.D F6,F0,F8
S.D F6,0(R1)
SUB.D F8,F10,F14
MUL.D F6,F10,F8

11. Type B/W RAW 1,2 F0 2,3 F6 4,5 F8 WAW 2,5 WAR 2,4 Struc ADDER
WAR and WAW Data Dependencies
Type
B/W
Register/FU
RAW
1,2 F0
2,3 F6
4,5 F8
WAW
2,5
WAR
2,4
Struc
ADDER
DIV.D F0,F2,F4
ADD.D F6,F0,F8
S.D F6,0(R1)
SUB.D F8,F10,F14
MUL.D F6,F10,F8

12. Name Dependencies
WAW and WAR dependencies are also called name dependencies: they do not carry a value between two instructions
Can be removed by avoiding use of the same name: rename the destination register whenever a new value is created
Both compiler (statically) and processor (dynamically) can do that

13. Register Renaming: Compiler
DIV.D F0,F2,F4
ADD.D F6,F0,F8
S.D F6,0(R1)
SUB.D F20,F10,F14
MUL.D F21,F10,F20
Only RAW or struc. hazards left

14. Dynamic Register Renaming
Use some architecture invisible registers for renaming, called rename registers to avoid WAW.
Read and keep a copy of available operands at the time of issue, this will avoid WAR. The values are stored in reservation station.

15. Tomasulo’s Algorithm Tag FP ADD Wait for Operands Wait for Operands EX
LD/ST
Wait for Operands
Wait for Operands EX
TAC
Mem
Access
Mem
Access
DATA
Register FILE
Tag
Wait for Operands
Wait for Operands
Wait for Operands EX
Integer
Integer
CDB
CDB
ISSUE/ Rename to RS
ISSUE/ Rename to RS
FP ADD FP
Wait for Operands
Wait for Operands
Wait for Operands A 1 A 1 A 2 A 2 A 3 A 3 A 4 A 4
Register FILE
Check for RS
Wait for Operands
Wait for Operands
Wait for Operands M 1 M 1 M 2 M 2 .. .. M 7 M 7
Wait for Operands
Wait for Operands
Wait for Operands
Divide
Divide
Check for RAW

16. MIPS FP Unit Using Tomasulo’s Algorithm
From Instruction Unit
FP registers
Instruction Queue
Load / Store Unit
FP Operations
Operand Busses
Address unit
Stop Buffers
Reservation Stations
Address
Data
FP multipliers
Memory unit
FP Adders
Common Data Bus (CDB)

17. Structure of Reservation Station
Qj,Qk: Like scoreboard
Vj, Vk: Contains values of two operands. Value are valid if Qj and Qk is zero
Busy
OpCode
A: For Target address TA or Imm value
Registers have Qi field as before

18. Tomasulo’s Example Write j k complete Result F6 R2 1 3 4 F2 R3 2 5 F0
Instruction status
Execution
Write
instruction j k
issue
complete
Result
L.D F6
34+ R2 1 3 4 F2
45+ R3 2 5
MUL.D F0 F4 15 16
SUB.D F8 7 8
DIV.D
F10 55 57
ADD.D 6 10 11