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Generating the “Rectify” code (C++ and assembly code)

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Presentation on theme: "Generating the “Rectify” code (C++ and assembly code)"— Presentation transcript:

1 Generating the “Rectify” code (C++ and assembly code)
Prelaboratory assignment information

2 Concepts Concepts of C++ “stubs” Forcing the test to fail
Generating valid “C++ code” to satisfy the tests Need for “name mangling” for overloaded functions How do you find out the name mangled name so it can be used in assembly code Learning just enough TigerSHARC assembly code to make things “work” 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

3 “C++ stub” Just enough information to satisfy the compiler
#include <stdio.h> #include <string.h> #include <stdlib.h> int *HalfWaveRectifyDebug(int initial_array[], int final_array[], int N) { return NULL; } 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

4 Integer rectify – force the tests to fail --- Test of the test
11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

5 Passing integer rectify
11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

6 Add the “ASM” tests Want link to fail to find mangled name
Name mangled function name 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

7 Generate assembly code
Do the code in steps, attempting to satisfy one test at a time Learn “the assembler” in steps Get “some idea” of the issues we need to learn about as we go along Just enough knowledge “to get things to work” Worry about full details later 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

8 Add ASM code stub Lab1/HalfWaveRectifyASMint.asm
11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

9 Where failed within Test file
11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

10 What we have learned We passed the “very general” test
Managed to call and return from an assembly code and did not crash the system We passed some specific tests in the test file “by accident” Which tests and why did they pass? CJUMP – is the “way to return” from an assembly code function to “C++” Instruction format is interesting nop; nop; nop;; ; separate instructions executed together cjump;; ;; indicates the end of an “grouped” instruction When jumps are involved, TigerSHARC seems to prefer code that involves “four 32-bit instruction: because of “BTB requirement” 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

11 More detailed look at the code
As with 68K needs a .section But name and format different As with 68K need .align statement Is the “4” in bytes (8 bits) or words (32 bits) As with 68K need .global to tell other code that this function exists Single semi-colons Double semi-colons Start function label End function label Label format similar to 68K Needs leading underscore and final colon 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

12 Need to know How do we return “an integer pointer”
Need to look at “C++” manual for coding conventions As with 68K expect to have Volatile registers – function variate registers, that DON’T need to be conserved Non-volatile registers – function invariate registers, that DO need to be conserved 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

13 Return registers There are many, depending on what you need to return
Here we need to use J8 Many registers available – need ability to control usage J0 to J31 – registers (integers and pointers) (SISD mode) XR0 to XR31 – registers (integers) (SISD mode) XFR0 to XFR31 – registers (floats) (SISD mode) Did I also mention I0 to U31 – registers (integers and pointers) (SISD mode) YR0 to YR31 , YFR0 to YFR31 (SIMD mode) XYR, YXR and R registers (SIMD mode) And also the MIMD modes And the ……. #define return_pt_J8 J // J8 is a VOLATILE register 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

14 Using J8 for returned int * value
Now passing this test “by accident Should be conditionally passing back NULL 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

15 Conditional tests Need to code – returning a NULL or the starting address of the final array int *HalfWaveRectifyRelease(int initial_array[ ], int final_array[ ], int N) if ( N < 1) return_pt = NULL; else /* after some calculations */ return_pt = &final[ ]; Questions to ask the instruction manual How are parameters passed to us? On the stack (as with 68K) or in registers / stack (as with MIPS)? – answer turns out to be more like MIPS How do you do an IF? How do you do conditional jumps? 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

16 Parameter passing Spaces for first four parameters present on the stack (as with 68K) But the first four parameters are passed in registers (J4, J5, J6 and J7 most of the time) (as with MIPS) The parameters passed in registers are often stored into the spaces on the stack (like the MIPS) when assembly code functions call assembly code functions J4, J5, J6 and J7 are volatile registers 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

17 Coding convention // int *HalfWaveRectifyRelease(int initial_array[ ],
// int final_array[ ], int N) #define initial_pt_inpar1 J4 #define final_pt_inpar2 J5 #define M_J6_inpar J6 #define return_pt_J J8 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

18 Doing an IF (N < 1) JUMP type of instruction
68K version CMP.L #1, D ; Performs D1 – 1 and sets ; condition code flag BLT ELSE ; Branch if result of D1 – 1 < ; BLE is a branch if less than ; zero instructions not on D1 < 1 TigerSHARC version COMP(N_inpar3, 1);; // Perform N – 1 test IF JLT, JUMP ELSE;; // Use of comma , and semi-colons ;; Same possible error on BOTH processors 68K which BLE, BLT or BGT? TigerSHARC – which JLE, JLT or NJLE? 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

19 Note END_IF not defined and not yet recognized as an error
ELSE is a KEYWORD Missing ;; means all these instructions are joined into “1-line” of more than 4 instructions Note END_IF not defined and not yet recognized as an error 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

20 Why is ELSE a keyword IF JLT; ELSE, J1 = J2 + J3; // Conditional execution ELSE, XR1 = XR2 + XR3; // Conditional YFR1 = YFR2 + YFR3;; // Unconditional IF JLT; DO, J1 = J2 + J3; // Conditional execution DO, XR1 = XR2 + XR3; // Conditional D0, YFR1 = YFR2 + YFR3;; // Unconditional I think I have also seen a IF, DO, ELSE instruction that can be used under special circumstances 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

21 Jumps can be predicted to happen (default) Quad stuff issue
Personally, because of name mangling issues, I cut-and-paste function name into labels Two issues Jumps can be predicted to happen (default) Quad stuff issue 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

22 QUAD and predicted jumps
Apparently both predicted and unpredicted jumps All jumps very disruptive to the TigerSHARC pipeline Uses something called “Branch Target Buffer” (BTB) to assist in overcome this. Saw this on AMD RISC processor Probably a 4 instructions–per-line cache so that jumps need to have 4 instructions between them to work 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

23 But at this stage “best” is not needed “working” is needed
Not the best solution But at this stage “best” is not needed “working” is needed 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

24 The code was not exactly what we designed (C++ equivalent) – refactor and retest after the refactoring NEXT STEP 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

25 Exercise – code the following as a software loop – follow 68K approach
extern “C” int CalculateSum(void) { int sum = 0; for (int count = 0; count < 6; count++) { sum = sum + count; } return sum; extern “C” – means that this function is “C” compatible rather than “C++”. No overloading (requiring name-mangling) permitted 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

26 Reminder – software for-loop becomes “while loop” with initial test
extern “C” int CalculateSum(void) { int sum = 0; int count = 0; while (count < 6) { sum = sum + count; count++; } return sum; Do line by line translation 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada

27 Concepts Concepts of C++ “stubs” Forcing the test to fail
Generating valid “C++ code” to satisfy the tests Need for “name mangling” for overloaded functions How do you find out the name mangled name so it can be used in assembly code Learning just enough TigerSHARC assembly code to make things “work” 11/15/2018 TigerSHARC assemble code 1, M. Smith, ECE, University of Calgary, Canada


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