1. CMOS VLSI Design Chapter 1: Introduction
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adapted for ECE403 & ECE553 by Duncan Elliott
Weste&Harris

2. Introduction Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
This chapter: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
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3. Where does this course fit in?
ECE 310 Introduction to Digital Logic Design
ECE 304 Digital Electronics
ECE 410 Advanced Digital Logic Design
ECE 403 Integrated Circuit Design
ECE 450 Nanoscale Phenomena in Electronic Devices
ECE 457 Microfabrication and Devices
ECE 413 Computer Aided Design of Nanoscale Systems
ECE 455 Engineering of Nanobiotechnological Systems
ECE 456 Introduction to Nanoelectronics
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4. Where does this course fit in in the grad calendar
ECE 511 Digital ASIC Design (alternative to ECE 410)
ECE 512 Digital System Testing and Design for Testability
ECE 547 Fundamentals of Solid State Devices
ECE 553 Digital Integrated Circuit Design
ECE 551 Design of CMOS Analog Integrated Circuits
ECE 571 Optical and Quantum Electronics
ECE 578 Advanced Mircowave and Millimeter-wave Circuits
ECE 651 Design of CMOS Radio-Frequency Integrated Circuits
ECE 558 Microfabrication and Nanofabrication Topics I
ECE 559 Microfabrication and Nanofabrication Topics II
ECE 658 Microsensors and Microelectromechanical Systems
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5. Silicon Lattice Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
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6. chapter 1

7. Dopants Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
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8. p-n Junctions
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction
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9. nMOS Transistor Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS) capacitor
Even though gate is
no longer made of metal and different insulators
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10. nMOS Operation Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
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11. nMOS Operation Cont. When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain, transistor is ON
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12. pMOS Transistor Similar, but doping and voltages reversed
Body tied to positive voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
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13. Power Supply Voltage GND = VSS = 0 V In 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 5.0, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … 450V
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14. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain
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15. CMOS Inverter A Y 1
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16. CMOS Inverter A Y 1
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17. CMOS Inverter A Y 1
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18. CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
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19. Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
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20. A Future Problem Set Find in the previous slide:
an NPN bipolar transistor
a PNP
an SCR
a way to stop this chip from exploding (CMOS latch-up)
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21. Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
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22. Inverter Mask Set Transistors and wires are defined by masks
Cross-section taken along dashed line
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23. Detailed Mask Views Six masks n-well thin oxide (not shown)
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
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24. Fabrication Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
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25. Fabrication Steps Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
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26. Oxidation Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
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27. Photoresist Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
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28. Lithography Expose photoresist through n-well mask
Strip off exposed photoresist
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29. Etch Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
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30. Strip Photoresist Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
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31. n-well n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
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32. Strip Oxide Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
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33. Polysilicon Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
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34. Polysilicon Patterning
Use same lithography process to pattern polysilicon
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35. Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
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36. N-diffusion Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing
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37. N-diffusion cont. Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
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38. N-diffusion cont. Strip off oxide to complete patterning step
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39. P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
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40. Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
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41. Metalization Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
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42. Recall - Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
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43. & Detailed Mask Views Six masks n-well Polysilicon n+ diffusion
p+ diffusion
Contact
Metal
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44. Layout Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Can normalize for feature size when describing design rules (quick and wasteful): can express rules in terms of l = f/2
E.g. l = 45nm in 90nm process
Production chips use nm design rules
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45. Simplified Design Rules
Conservative rules for quick area-inefficient designs
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46. Gate Layout Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
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47. Example: Inverter
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48. CMOS NAND Gate A B Y 1
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49. CMOS NAND Gate A B Y 1
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50. CMOS NAND Gate A B Y 1
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51. CMOS NAND Gate A B Y 1
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52. CMOS NAND Gate A B Y 1
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53. CMOS NOR Gate A B Y 1
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54. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0 ?
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55. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
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56. Example: NAND3 Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
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57. Stick Diagrams Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
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58. Wiring Tracks A wiring track (pitch) is the space required for a wire
4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
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59. Well spacing Wells must surround transistors by 6 l
Implies 12 l between opposite transistor flavors
Leaves room for one wire track
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60. Example: O3AI
Sketch a schematic & stick diagram for O3AI
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61. Example: O3AI
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62. Example: O3AI
Sketch a stick diagram for O3AI
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63. Example: O3AI Sketch a stick diagram for O3AI and estimate area
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64. Process Corners - Briefly
Operating Conditions
VDD
Temperature
Parameter Variation
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65. Parameter Variation Transistors have uncertainty in parameters
Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)
Leff: short
Vt: low
tox: thin
Slow (S): opposite
Not all parameters are independent
for nMOS and pMOS
Ch 2. MOS Theory

66. Summary MOS Transistors are stacks of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start designing schematics and layout for a simple chip!
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67. Outline A Brief History Pass Transistors CMOS Latches & Flip-Flops
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68. Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
See Crystal Fire
by Riordan, Hoddeson
AT&T Archives. Reprinted with permission.
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69. Courtesy Texas Instruments
A Brief History
1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2010
Intel Core i7 mprocessor
2.3 billion transistors
64 Gb Flash memory
> 16 billion transistors
Courtesy Texas Instruments
[Trinh09]
© 2009 IEEE.
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70. Growth Rate 53% compound annual growth rate over 50 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
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71. Annual Sales >1019 transistors manufactured in 2008
1 billion for every human on the planet
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72. Transistor Types Bipolar transistors npn or pnp silicon structure
Small current into very thin base layer controls large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between source and drain
Low power allows very high integration
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73. MOS Integrated Circuits
1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
Intel Museum.
Reprinted with permission.
[Vadasz69]
© 1969 IEEE.
Intel bit SRAM
Intel bit mProc
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74. Technology Trend – Moore’s Law
Extracted From: G. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, Apr
Extracted From:
In 1965, Gordon Moore Predicted that the Transistor count will double every 1.5 years.

75. Feature Size Minimum feature size shrinking 30% every 2-3 years
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76. Technology Trend – Moore’s Law
Levels of Integration of Chips
Small-Scale Integration (SSI)
Circuits with less than 10 gates.
Medium-Scale Integration (MSI)
Circuits with number of gates up to 1000.
Large-Scale Integration (LSI)
Circuits with number of gates up to 10,000.
Very Large-Scale Integration (VLSI)
Circuits with number of gates more than 10,000.

77. Technology Trend – Moore’s Law MOS Oxide Thickness TOX (A)
The Transistor minimum feature size is reducing over years. This is accompanied by exponential reduction in the MOS oxide thickness and consequently dictates reducing the supply voltage.
G. E. Moore, “No exponential is forever: but "Forever" can be delayed!”, ISSCC ‘03
MOS Oxide Thickness TOX (A)
Power Supply (V)

78. Technology Trend – Moore’s Law Average Transistor Cost ($)
The Transistor cost reduces (10 microcents) as technology advances while consuming lower power and supporting higher frequencies.

79. Recent Trends in Digital IC Design
ISSCC 2016 Trend for Clock Frequency Scaling
Extracted From the ISSCC Website:

80. Recent Trends in Digital IC Design ISSCC 2016 Trend for Data Rates
Extracted From the ISSCC Website:

81. Recent Trends in Digital IC Design
ISSCC 2016 Trend for Memory
Extracted From the ISSCC Website:

82. Recent Trends in Digital IC Design
Examples from Recently Published Work
Fayneh et al, Intel, ISSCC 2016
A 14 nm 6th Generation Core Processor
Song et al, Samsung, ISSCC 2016
A 10 nm 128Mb SRAM

83. Complementary CMOS Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float) 1
Pull-down ON
X (crowbar)
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84. Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON
Parallel: either can be ON
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85. Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel
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86. Compound Gates Compound gates can do any inverting function Ex:
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87. Example: O3AI
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88. Signal Strength Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network
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89. Pass Transistors
Transistors can be used as switches
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90. Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
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91. Tristates Tristate buffer produces Z when not enabled EN A Y Z 1Z 1
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92. Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
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93. Tristate Inverter Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
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94. Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1X 1
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95. Gate-Level Mux Design
How many transistors are needed? 20
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96. Transmission Gate Mux Nonrestoring mux uses two transmission gates
Only 4 transistors
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97. Inverting Mux Inverting multiplexer Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
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98. 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
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99. D Latch When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
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100. D Latch Design
Multiplexer chooses D or old Q
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101. CMOS VLSI Design Chapter 1: Introduction CMOS Design Flow

102. Outline Design Partitioning MIPS Processor Design Flow Example
Architecture
Microarchitecture
Logic Design
Circuit Design
Physical Design
Fabrication, Packaging, Testing
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103. Mental Exercise Sketch a stick diagram for a 4-input NOR gate
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104. Software vs. ASIC vs. Custom
Technologies
Software & microcontroller
Field Programmable Gate Array (FPGA)
Application Specific Integrated Circuit (ASIC)
Full Custom Integrated Circuit
Tradeoffs?
design time
manufacturing time
capital cost
volume cost
speed/power/area
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105. Hardware Advantages
Custom hardware can typically be designed to be faster than software solutions
e.g. backbone network switches
Hardware is essential to make the connections to processors
interfaces
bus & memory controllers
Reliability – hardware can keep doing critical operations after the processor crashes on account of an unhandled exceptions, or permanent failures
failsafe circuits – e.g. pacemaker
watchdog circuits
embedded processor pulses a happy signal, else is reset
stoplight - fail to blinking red all directions
Smaller than a processor, therefore less to go wrong, hopefully.
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106. Compromise – System on a Chip (SoC)
On one chip
use software & microprocessors where it makes sense
use hardware where it makes sense
Design reuse
Build a chip out of commercially available reusable designs “IP Cores”
Many companies exist solely to sell these IP Cores
Free IP Cores are avail with open licences (e.g. GNU)
Examples in
free VHDL designs, components, chips
Designing a chip can be like choosing components (standard chips) to go on a printed circuit board
Still have the flexibility to add full custom components to portions of your chip design
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107. SOC
figure courtesy of ARM
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108. Coping with Complexity
How to design System-on-Chip?
Many millions to billions of transistors
Tens to hundreds of engineers
Structured Design
Design Partitioning
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109. Structured Design Hierarchy: Divide and Conquer
Recursively break system into modules
Regularity
Reuse modules wherever possible
Eg. Standard cell library
Modularity: well-formed interfaces
Allows modules to be treated as black boxes
Locality
Physical and temporal
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110. Design Partitioning Architecture: User’s perspective, what does it do?
Instruction set, registers
MIPS, x86, Alpha, PIC, ARM, …
Microarchitecture
Single cycle, multicycle, pipelined, superscalar?
Logic: how are functional blocks constructed
Ripple carry, carry lookahead, carry select adders
Circuit: how are transistors used
Complementary static CMOS, pass transistors, domino
Physical: chip layout
Datapaths, memories, random logic
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111. Gajski Y-Chart
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112. In the beginning (the evolution of design flow)
Build
Debug
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113. Let’s think about this first
Plan (hand drawn schematic)
Verify by hand
Build
Debug
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114. Can Computers Do Some of the Grunt Work?
Plan (CAD schematic / netlist / VHDL)
Simulate (by machine)
Build
Debug
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115. ... and some of the Optimization
Structural Design (CAD schematic / netlist / VHDL)
Verification
Physical Design
Implement (configure / manufacture)
Test
Verification includes
simulation
static timing analysis
rule checks
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116. Now Design at a Higher Level
Behavioural Description (VHDL)
Verification
Synthesis (netlist out)
Physical Design
Implement (configure / manufacture)
Test
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117. A Larger Design Flow Behavioural Description Test Generation
Verification
Synthesis
Physical Design
Verification Compare
Implement (configure / manufacture)
Test
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118. Is That all There is to a Design Flow?
NO, there’s lots more tools ... [from Cadence]
Logic synthesis
Design-for-test Insertion
Initial gate-level synthesis
Chip floorplan
Timing-driven placement
Static timing analysis
Clock tree generation
Placement-based optimization
Timing driven routing
Parasitic extraction/analysis
Logical equivalence check (more than LVS)
Static timing verification
Physical verification (including DRC)
Formal verification
Not including behavioural simulation, netlist simulation, post-layout simulation, etc.
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119. Design Techniques Design Partitioning MIPS Processor Example
Architecture
Microarchitecture
Logic Design
Circuit Design
Physical Design
Fabrication, Packaging, Testing
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120. MIPS Architecture Example: subset of MIPS processor architecture
Drawn from Patterson & Hennessy
MIPS is a 32-bit architecture with 32 registers
Consider 8-bit subset using 8-bit datapath
Only implement 8 registers ($0 - $7)
$0 hardwired to
8-bit program counter
9 instructions
Illustrates the key concepts in VLSI design
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121. MIPS Microarchitecture
Multicycle marchitecture ( [Paterson04], [Harris07] )
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122. Multicycle Controller
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123. Logic Design Start at top level
Hierarchically decompose MIPS into units
Top-level interface
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124. Block Diagram
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125. Hierarchical Design
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126. HDLs Hardware Description Languages Widely used in logic design
Verilog and VHDL
Describe hardware using code
Document logic functions
Simulate logic before building
Synthesize code into gates and layout
Requires a library of standard cells
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127. Verilog Example module fulladder(input a, b, c, output s, cout);
sum s1(a, b, c, s);
carry c1(a, b, c, cout);
endmodule
module carry(input a, b, c,
output cout)
assign cout = (a&b) | (a&c) | (b&c);
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128. VHDL Example
library ieee; use ieee.std_logic_1164.all; -- level sensitive latch - active high entity latch is port( d, enable: in std_logic; q : out std_logic ); end entity latch; architecture behavioural of latch is begin latch: process (d, enable) is if enable = '1' then q <= d; -- data flows through end if; end process latch; end behavioural;
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129. Circuit Design How should logic be implemented?
NANDs and NORs vs. ANDs and ORs?
Fan-in and fan-out?
How wide should transistors be?
These choices affect speed, area, power
Logic synthesis makes these choices for you
Good enough for many applications
Hand-crafted circuits are still better
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130. Example: Carry Logic Transistors? Gate Delays?
assign cout = (a&b) | (a&c) | (b&c);
Transistors? Gate Delays?
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131. Gate-level Netlist module carry(input a, b, c, output cout)
wire x, y, z;
and g1(x, a, b);
and g2(y, a, c);
and g3(z, b, c);
or g4(cout, x, y, z);
endmodule
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132. Transistor-Level Netlist
module carry(input a, b, c,
output cout)
wire i1, i2, i3, i4, cn;
tranif1 n1(i1, 0, a);
tranif1 n2(i1, 0, b);
tranif1 n3(cn, i1, c);
tranif1 n4(i2, 0, b);
tranif1 n5(cn, i2, a);
tranif0 p1(i3, 1, a);
tranif0 p2(i3, 1, b);
tranif0 p3(cn, i3, c);
tranif0 p4(i4, 1, b);
tranif0 p5(cn, i4, a);
tranif1 n6(cout, 0, cn);
tranif0 p6(cout, 1, cn);
endmodule
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133. SPICE Netlist .SUBCKT CARRY A B C COUT VDD GND
MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P
MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P
MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P
MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P
MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P
MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P
MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P
MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P
MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P
MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P
CI1 I1 GND 2FF
CI3 I3 GND 3FF
CA A GND 4FF
CB B GND 4FF
CC C GND 2FF
CCN CN GND 4FF
CCOUT COUT GND 2FF
.ENDS
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134. Physical Design Floorplan Standard cells Place & route Datapaths
Slice planning
Area estimation
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135. Area Estimation Need area estimates to make floorplan
Compare to another block you already designed
Or estimate from transistor counts
Budget room for large wiring tracks
Your mileage may vary
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136. MIPS Floorplan
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137. MIPS Layout
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138. Standard Cells Uniform cell height Uniform well height
M1 VDD and GND rails
M2 Access to I/Os
Well / substrate taps
Exploits regularity
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139. Synthesized Controller
Synthesize HDL into gate-level netlist
Place & Route using standard cell library
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140. Current Std Cell Routing
6 – 9 metal layers instead of 2
most routing over standard cells
standard cell power rails abutted
80-95% cell density (sometimes 100%) in core
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141. Full Custom – Pitch Matching
Synthesized controller area is mostly wires
Design is smaller if wires run through/over cells
Smaller = faster, lower power as well!
Design snap-together cells for datapaths and arrays
Plan wires into cells
Connect by abutment
Exploits locality
Takes lots of effort
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142. MIPS Datapath 8-bit datapath built from 8 bitslices (regularity)
Zipper at top drives control signals to datapath
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143. Slice Plans Slice plan for bitslice
Cell ordering, dimensions, wiring tracks
Arrange cells for wiring locality
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144. Custom vs. Synthesis
8-bit Implementations
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145. Design Verification Fabrication is slow & expensive
MOSIS 0.6mm: $1000, 3 months
65 nm: $3M, 1 month
Debugging chips is very hard
Limited visibility into operation
Prove design is right before building!
Logic simulation
Ckt. simulation / formal verification
Layout vs. schematic comparison
Design & electrical rule checks
Verification is > 50% of effort on most chips!
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146. Fabrication & Packaging
Tapeout final layout
Fabrication
6, 8, 12” wafers
Optimized for throughput,
not latency (10 weeks!)
Cut into individual dice
Packaging
Bond gold wires from die I/O pads to package
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147. Testing Test that chip operates Design errors Manufacturing errors
A single dust particle or wafer defect kills a die
Yields from 90% to < 10%
Depends on die size, maturity of process
Test each part before shipping to customer
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148. Berkeley RISC VLSI course project 1981 tape-out
44,500 transistors, 2 m IC process
Simulated performance > expensive VAX 11/780 department server
31 instructions
first 32-bit processor on one die
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149. Berkeley RISC Designers
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150. MIPS R3000 Processor 32-bit 2nd generation commercial processor (1988)
Led by John Hennessy (Stanford, MIPS Founder)
32-64 KB Caches
1.2 mm process
111K Transistor
Up to MHz
66 mm2 die
145 I/O Pins
VDD = 5 V
4 Watts
SGI Workstations
chapter 1