1. The Microprosesor Architecture & Hardware Specification
Prima Dewi Purnamasari
Microprocessor
Electrical Engineering Department
Universitas Indonesia

2. 8086/8088 Hardware Specifications
Pin-Outs & Pin Functions
Clock generator
Bus buffering and latching
Bus timing
Ready and wait state
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3. Intel x86 First Generation Microprocessor
The term x86 refers to a family of instruction set architectures based on the Intel 8086 CPU.
The 8086 was launched in 1978 as a fully 16-bit extension of Intel's 8-bit based 8080 microprocessor and also introduced segmentation to overcome the 16-bit addressing barrier of such designs.
The Intel 8088, released in 1979, was a slightly modified chip with an external 8-bit data bus (allowing the use of cheaper and fewer supporting logic chips), and is notable as the processor used in the original IBM PC.
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4. Pin-Outs 8086 is a 16-bit microprocessor with 16-bit data bus
Therefore:
8086 has pin connections AD0–AD15
8088 has pin connections AD0–AD7
Data bus width is the only major difference.
thus 8086 transfers 16-bit data more efficiently
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5. Fig. 9-1 8088 vs 8086 in MAX {MIN} mode
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6. Figure  (a) The pin-out of the 8086 in maximum mode; (b) the pin-out of the 8086 in minimum mode. Both are packaged in 40-pin dual in-line packages (DIPs)
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7. The Pin-Out(cont’d) The minor difference in one of the control signals
8086 has an M/IO pin
8088 has an IO/M pin
The only other hardware difference appears on pin 34 of both chips :
on the 8080, it is an SS0 pin
on 8086, it is BHE/S7 pin
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8. Power Supply Requirements
Both microprocessors require +5.0 V with a supply voltage tolerance of ±10 percent.
8086 uses a maximum supply current of 360 mA
8088 draws a maximum of 340 mA
Both microprocessors operate in ambient temperatures of between 32° F and 180° F.
80C88 and 80C86 are CMOS versions that require only 10 mA of power supply current.
and function in temperature extremes of –40° F through +225° F
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9. DC Characteristics
It is impossible to connect anything to a microprocessor without knowing input current requirement for an input pin.
and the output current drive capability for an output pin
This knowledge allows hardware designers to select proper interface components for use with the microprocessor
without the fear of damaging anything
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10. Input & Output Characteristics
Table 9-1. Input Characteristics
Logic level
Voltage
Current
0.8V max
±10 µA max 1
2.0V min
Table 9-2. Output Characteristics
Logic level
Voltage
Current
0.45V max
±2.0 µA max 1
2.4 min
-400 µAmax
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11. No more than 10 loads of any type should be connected to an output pin without buffering
if this factor is exceeded, noise will begin to take its toll in timing problems
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12. Pin Connections Naming
Pin with no upper-line (no invert symbol) does its job when it has logic 1.
E.g.: Pin INTR  request a hardware interrupt when logic 1
Pin with upper-line (with invert symbol) does its job when it has logic 0
E.g.: Pin RD  When read signal is logic 0, the data bus is receptive to data from memory or I/O devices
Pin with 2 inverted functions does its job according to the name
E.g.: Pin IO/M (in 8088) selects memory when logic 0 or I/O when logic 1.
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13. Pin Connections AD15 - AD8  8086 address/data bus multiplexed
Function as address when ALE (address latch enable)= 1
Function as data when ALE = 0
A15 - A8  8088 address bus
AD15 - AD8  8086 address/data bus multiplexed
Similar to point 1
A19/S6 - A16/S3  Address/status bus bits are multiplexed to provide address signals A19–A16 and status bits S6–S3.
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14. Pin Connections (self reading)
RD  When read signal is logic 0, the data bus is receptive to data from memory or I/O devices
READY  Inserts wait states into the timing.
0 = enters into wait states and remains idle
1 = no effect on the operation
INTR  Interrupt request is used to request a hardware interrupt.
NMI  The non-maskable interrupt input is similar to INTR but does not check IF (interrupt flag).
The TEST pin is an input that is tested by the WAIT instruction.
If logic 1, WAIT instruction waits for TEST to become a logic 0.
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15. Pin Connections (self reading)
RESET Causes the microprocessor to reset itself if held high a minimum of four clocking periods.
when 8086/8088 is reset, it executes instructions at memory location FFFFOH
also disables future interrupts by clearing IF flag
CLK  The clock pin provides the basic timing signal.
duty cycle of 33 % (high for one third of clocking period, low for two thirds)
VCC  This power supply input provides a +5.0 V, ±10 % signal to the microprocessor.
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16. Pin Connections (self reading)
GND  The ground connection is the return for the power supply.
8086/8088 microprocessors have two pins labeled GND—both must be connected to ground for proper operation
MN/MX  Minimum/maximum mode pin selects either minimum or maximum mode operation.
if minimum mode selected, the MN/MX pin must be connected directly to +5.0 V
BHE S7  The bus high enable pin is used in 8086 to enable the most-significant data bus bits (D15–D8) during a read or a write operation. The state of S7 is always a logic 1.
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17. Minimum Mode Pins (self reading)
Minimum mode operation is obtained by connecting the MN/MX pin directly to +5.0 V.
do not connect to +5.0 V through a pull-up register; it will not function correctly
IO/M (8088) or M/IO (8086) pin selects memory or I/O.
WR  indicates 8086/8088 is outputting data to a memory or I/O device.
INTA  The interrupt acknowledge signal is a response to the INTR input pin.
ALE  Address latch enable shows the 8086/8088 address/data bus contains an address.
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18. Minimum Mode Pins (self reading)
DT/R  The data transmit/receive signal shows that the microprocessor data bus is transmitting (DT/R = 1) or receiving (DT/R = 0) data.
DEN  Data bus enable activates external data bus buffers.
HOLD  Hold input requests a direct memory access (DMA).
HLDA Hold acknowledge indicates the 8086/8088 has entered the hold state.
SS0 The SS0 status line is equivalent to the S0 pin in maximum mode operation. Signal is combined with IO/M and DT/R to decode the function of the current bus cycle.
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19. Maximum Mode Pins (self reading)
In order to achieve maximum mode for use with external coprocessors, connect the MN/MX pin to ground.
S2, S1, and S0 Status bits indicate function of the current bus cycle. Normally decoded by the 8288 bus controller
RQ/GT1  The request/grant pins request direct memory accesses (DMA) during maximum mode operation.
LOCK  The lock output is used to lock peripherals off the system.
QS1 and QS0 The queue status bits show the status of the internal instruction queue.
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20. Clock Generator (8284A)
It is an ancillary component to the 8086/8088 microprocessors.
With no clock generator, many circuits would be required to generate the clock (CLK).
The 8284A provides the following basic functions or signals :
clock generation
RESET synchronization
READY synchronization
a TTL level peripheral clock signal
Pin Functions (self study)
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21. Figure 9–2 The pin-out of the 8284A clock generator.
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22. Figure 9–3 The internal block diagram of the 8284A clock generator.
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23. Figure 9–4  The clock generator (8284A) and the 8086 and 8088 microprocessors illustrating the connection for the clock and reset signals. A 15 MHz crystal provides the 5 MHz clock for the microprocessor.
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24. Bus Buffering and Latching
The address/data bus of the 8086/8088 is multiplexed (shared) to reduce the number of pins required for the integrated circuit.
Before 8086/8088 can be used with memory or I/O interfaces, their multiplexed buses must be demultiplexed.
the hardware designer must extract or demultiplex information from these pins
Memory & I/O require the address remain valid and stable throughout a read/write cycle.
If buses are multiplexed, the address changes at the memory and I/O, causing them to read or write data in the wrong locations
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25. Demultiplexing the 8088
The latches, which are like wires whenever the address latch enable pin (ALE) becomes a logic 1, pass the inputs to the outputs.
After a short time, ALE returns to logic 0 causing the latches to remember inputs at the time of the change to a logic 0.
This yields a separate address bus with connections A19–A0.
these allow 8088 to address 1Mb of memory
The separate data bus allows it to be connected to any 8-bit peripheral device or memory component.
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26. Figure 9–5  The 8088 microprocessor shown with a demultiplexed address bus. This is the model used to build many 8088-based systems.
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27. Demultiplexing the 8086
Fig 9–6 illustrates a demultiplexed 8086 with all three buses:
address (A19–A0 and BHE )
data (D15–D0),
control (M/IO,RD, and WR )
Here, the memory and I/O system see the 8086 as a device with:
a 20-bit address bus
6-bit data bus
and a three-line control bus
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28. Figure 9–6  The 8086 microprocessor shown with a demultiplexed address bus. This is the model used to build many 8086-based systems.
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29. The Buffered System
If more than 10 unit loads are attached to any bus pin, the entire system must be buffered.
Buffer output currents have been increased so that more TTL unit loads may be driven.
A fully buffered signal will introduce a timing delay to the system.
No difficulty unless memory or I/O devices are used which function at near maximum bus speed.
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30. Figure 9–7 A fully buffered 8088 microprocessor.
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31. Figure 9–8 A fully buffered 8086 microprocessor.
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32. Bus Timing Timing in general:
The 8086/8088 microprocessor use the memory and I/O in periods of time called bus cycles.
Each bus cycle = 4 system-clocking periods (Tstates).
newer microprocessors divide the bus cycle into as few as two clocking periods
If the clock is operated at 5 MHz, one 8086/8088 bus cycle is complete in 800 ns. (= 1÷ (5 x 106) )
basic operating frequency for these processors
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33. Bus Cycle During T1: During T2:
address of memory or I/O location is sent out via the address bus and the address/data bus connections.
control signals are also output, indicating whether the address bus contains a memory address or an I/O device (port) number
During T2:
RD or WR signal, DEN,
in case of WRITE, data to be written appear on the data bus,
READY is sampled at the end of T2.
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34. Bus Cycle During T3 During T4 Data are written
if low at T2, T3 becomes a wait state (Tw)
this clocking period is provided to allow the memory time to access data
In case of READ, the data bus is sampled at the end of T3.
During T4
Data are written
All bus signals are deactivated in preparation for the next bus cycle
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35. Sample for WRITE operation (to memory)
outputs the memory address on the address bus
outputs the data to be written on the data bus
issues a write (WR) to memory
and IO/M= 0 for 8088 and IO/M = 1 for 8086
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36. Sample for READ operation (from memory)
outputs the memory address on the address bus
issues a read memory signal (RD)
and accepts the data via the data bus
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37. READY and the WAIT STATE
READY input causes wait states for slower memory and I/O components. A wait state (Tw) is an extra clocking period, inserted between T2 & T3 that lengthens the bus cycle. If one wait state is inserted, then the memory access time is lengthened by one clocking period (200 ns) to 660 ns, normally 460 ns with a 5 MHz clock.
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38. Minimum Mode vs Maximum Mode
Minimum mode operation is similar to that of the Intel 8085A microprocessor, while maximum mode operation is new & specially designed for the operation of the arithmetic coprocessor
Minimum Mode Operation
it is obtained by connecting the mode selection pin MN/MX to +5.0V
the minimum mode allows the 8085A, 8 bit peripherals to be used with the 8086/8088 without any special considerations
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39. Minimum Mode vs Maximum Mode (cont’d)
Maximum Mode Operation
it is selected by grounding MN/MX
the maximum mode is used only when the system contains external coprocessors such as the 8087 arithmetic coprocessor
The 8288 Bus Controller
it must be used in the maximum mode to provide the control bus signals to the memory and I/O
this is because the maximum mode operation of the 8086/8088 removes some of the systems control signal lines in favor of control signals for the coprocessors
the 8288 reconstructs these removed control signals
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40. Microprocessor architecture
Internal microprocessor Architecture
Real Mode Memory Addressing
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41. Internal µP Architecture
The programming model of the 8086 through Core2 is considered program visible registers.
registers are used during programming and are specified by the instructions
Other registers are considered program invisible registers.
they are not addressable directly during applications programming, but may be used indirectly during system programming
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42. Figure 2–1  The programming model of the 8086 through the Core2 microprocessor including the 64-bit extensions.
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43. Naming Structure for x86 (including 64 bit registers)
General Purpose Registers (A, B, C, D)
Segment Registers (C, D, E, S, F, G)
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44. Pointers Registers (S, B), The
Pointers Registers (S, B), The ?PL registers are only available in 64-bit mode.
Index Registers (S, D)
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45. Instruction Pointer Register (I)
64-bit mode-only General Purpose Registers (R8, R9, R10, R11, R12, R13, R14, R15)
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46. RBX, addressable as RBX, EBX, BX, BH, BL.
Multipurpose Registers: The programming model of the 8086 through the Core2 microprocessor including the 64-bit extensions.
RAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH and AL).
used for instructions such as multiplication, division, and some of the adjustment instructions
In and above EAX may hold the offset address of a memory location
RBX, addressable as RBX, EBX, BX, BH, BL.
BX register (base index) sometimes holds offset address of a location in the memory system in all versions of the microprocessor
RCX, as RCX, ECX, CX, CH, or CL.
a (count) general-purpose register that also holds the count for various instructions (repeat, shift, rotate, loop)
RDX, as RDX, EDX, DX, DH, or DL.
a (data) general-purpose register
holds a part of the result from a multiplication or part of dividend before a division
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47. points to a memory (base pointer) location for memory data transfers
Multipurpose Registers: The programming model of the 8086 through the Core2 microprocessor including the 64-bit extensions.
RBP, as RBP, EBP, or BP.
points to a memory (base pointer) location for memory data transfers
RDI addressable as RDI, EDI, or DI.
often addresses (destination index) string destination data for string instructions
RSI used as RSI, ESI, or SI.
the (source index) register addresses source string data for the string instructions
like RDI, RSI also functions as a general- purpose register
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48. The 64 bit Registers
R8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled.
data are addressed as 64-, 32-, 16-, or 8-bit sizes and are of general purpose
Most applications will not use these registers until 64-bit processors are common.
the 8-bit portion is the rightmost 8-bit only
bits 8 to 15 are not directly addressable as a byte
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49. The 64 bit Registers Register size Override Bits accesses Example
7-0
MOV R19B, R10B
16 bits W
15-0
MOV R10W, AX
32 bits D
31-0
MOV R14D, R15D
64 bits -
63-0
MOV R13, R12
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50. 8086/8088 registers 8086/8088 is 16-bit microprocessor
It has 16-bit registers
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51. 8086/8088 Multipurpose Register
AX (accumulator)
for instructions (e.g., multiplication, division, and some of adjustment instructions)
may hold the offset address of a location in the memory
BX (base index)
sometimes hold the offset address of a location in the memory system
Can address memory data
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52. Multipurpose Register (cont’d)
CX (count)
Used to hold the count for some instructions, REP and LOOP.
Used to hold the offset of a data pointer.
DX (data)
Used to hold a portion of the result for MUL, of the operand for DIV.
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53. Multipurpose Register (cont’d)
BP (base pointer) points to a memory location
DI (destination index) addresses string destination data for the string instructions
SI (source index) addresses source string data for the string instructions
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54. Special Purpose Registers (cont’d)
IP (instruction pointer) points to the next instruction in a program and is used to find the next sequential instruction in a program located within the code segment
SP (stack pointer) addresses an area of memory called the stack
FLAGS indicate the condition of the micro-processor as well as control its operation
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55. Flags are upward-compatible from the 8086/8088 through Core2 .
RFLAGS -  The EFLAG and FLAG register counts for the entire 8086 and Pentium microprocessor family.
Flags are upward-compatible from the 8086/8088 through Core2 .
The rightmost five and the overflow flag are changed by most arithmetic and logic operations.
Flags never change for any data transfer or program control operation.
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56. O (overflow) occurs when signed numbers are added or subtracted.
C (carry) holds the carry after addition or borrow after subtraction. Also indicates error conditions
P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even parity.
A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction between bit positions 3 and 4 of the result.
Z (zero) shows that the result of an arithmetic or logic operation is zero.
S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction executes.
O (overflow) occurs when signed numbers are added or subtracted.
an overflow indicates the result has exceeded the capacity of the machine
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57. T (trap) The trap flag enables trapping through an on-chip debugging feature.
I (interrupt) controls operation of the INTR (interrupt request) input pin.
Enables or disables interrrupts
Contolled by STI and CLI instructions
D (direction) selects increment or decrement mode for the DI and/or SI registers.
Set by STD and cleared by CLD instructions
IOPL used in protected mode operation to select the privilege level for I/O devices. If I/O privelage level of a requesting device is higher, an iterrupt occurs (IOPL=00 highest; IOPL=00 lowest).
NT (nested task) flag indicates the current task is nested within another task in protected mode operation.
Self reading
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58. RF (resume) used with debugging to control resumption of execution after the next instruction.
VM (virtual mode) flag bit selects virtual mode operation in a protected mode system. VM is used to simulate DOS in the modern Windows environment.
AC, (alignment check) flag bit activates if a word or doubleword is addressed on a non-word or non-doubleword boundary.
VIF –(virtual interrupt) is a copy of the interrupt flag bit available to the Pentium 4
VIP (virtual interrupt pending) provides information about a virtual mode interrupt for Pentium.
used in multitasking environments to provide virtual interrupt flags
ID (identification) flag indicates that the Pentium microprocessors support the CPUID instruction.
CPUID instruction provides the system with information about the Pentium microprocessor
Self reading
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59. Segment Registers
Generate memory addresses when combined with other registers in the microprocessor.
Four or six segment registers in various versions of the microprocessor.
A segment register functions differently in real mode than in protected mode.
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60. DS (data) contains most data used by a program.
CS (code) segment holds code (programs and procedures) used by the microprocessor.
DS (data) contains most data used by a program.
Data are accessed by an offset address or contents of other registers that hold the offset address
ES (extra) an additional data segment used by some instructions to hold destination data.
SS (stack) defines the area of memory used for the stack.
stack entry point is determined by the stack segment and stack pointer registers
the BP register also addresses data within the stack segment
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61. FS and GS segments are supplemental segment registers available in 80386–Core2 microprocessors.
allow two additional memory segments for access by programs
Windows uses these segments for internal operations, but no definition of their usage is available.
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62. Real Mode Memory Addressing
80286 and above operate in either the real or protected mode.
Real mode operation allows addressing of only the first 1M byte of memory space—even in Pentium 4 or Core2 microprocessor.
the first 1M byte of memory is called the real memory, conventional memory, or DOS memory system
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64. Effective memory address = Segment address x 10H + offset adress
Segments and Offsets
Effective memory address =
Segment address x 10H + offset adress
The segment address defines the beginning address of any 64K-byte memory segment
The offset address selects any location within the 64KB memory segment (sometimes called displacement)
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65. Trivia: name the segment registers!
Figure 2–3  The real mode memory-addressing scheme, using a segment address plus an offset.
this shows a memory segment beginning at 10000H, ending at location IFFFFH
64K bytes in length
also shows how an offset address, called a displacement, of F000H selects location 1F000H in the memory
Trivia: name the segment registers!
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66. Once the beginning address is known, the ending address is found by adding FFFFH.
because a real mode segment of memory is64K in length
The offset address is always added to the segment starting address to locate the data.
Segment and offset address is sometimes written as segment_address:offset_address
E.g.: 1000:2000
a segment address of 1000H; an offset of 2000H
Memory address is 1000 x = 12000H
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67. Default Segment and Offset Registers
The microprocessor has rules that apply to segments whenever memory is addressed.
these define the segment and offset register combination
Address of an Instruction
The code segment register defines the start of the code segment.
The instruction pointer locates the next instruction within the code segment.
The address of the instruction is CS:IP
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68. Another of the default combinations is the stack.
stack data are referenced through the stack segment at the memory location addressed by either the stack pointer (SP/ESP) or the pointer (BP/EBP)
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69. Table 3-2 Default 16-bit segment and offset combinations
Special Purpose CS IP
Instruction address SS
SP or BP
Stack address DS
BX, DI, SI, an 8- or 16-bit number
Data address ES
DI for string instructions
String destination address
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70. a program can have more than four or six segments,
Figure 2–4  A memory system showing the placement of four memory segments.
a memory segment can touch or overlap if 64K bytes of memory are not required for a segment
think of segments as windows that can be moved over any area of memory to access data or code
a program can have more than four or six segments,
but only access four or six segments at a time
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71. area is indicated by a free-pointer maintained by DOS
a program placed in memory by DOS is loaded in the TPA at the first available area of memory above drivers and other TPA programs
area is indicated by a free-pointer maintained by DOS
program loading is handled automatically by the program loader within DOS
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72. Example: 1000H bytes for code 190H bytes for data 200H bytes for stack
Figure 2–5  An application program containing a code, data, and stack segment loaded into a DOS system memory.
Example:
Suppose an application program requires
1000H bytes for code
190H bytes for data
200H bytes for stack
CS: 090F -> end address 090F0H H = 0A0F0H
DS: 0A0F -> end address 0A0F0H + 190H = 0A280H
SS: 0A28 -> end addrss 0A280H + 200H = 0A480
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73. Segment and Offset Addressing Scheme Allows Relocation
Segment plus offset addressing allows DOS programs to be relocated in memory.
A relocatable program is one that can be placed into any area of memory and executed without change.
Relocatable data are data that can be placed in any area of memory and used without any change to the program.
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74. Because memory is addressed within a segment by an offset address, the memory segment can be moved to any place in the memory system without changing any of the offset addresses.
Only the contents of the segment register must be changed to address the program in the new area of memory.
Windows programs are written assuming that the first 2G of memory are available for code and data.
Microprocessor (c) Prima Dewi Purnamasari 2011
11/12/2018

75. Exercise—due 20/9/2011 Taken from Barry B. Brey 7th ed. Chapter 2:
Number1- 21
Chapter 9:
7, 9, 18, 29, 32, 35, 38
Do it in groups of 4
Answer it in PPT style (with sufficient explanation)
Print in handout view, submit to the teacher in class
Bring the softcopy, one or two of your groups should present it next week
Microprocessor (c) Prima Dewi Purnamasari 2011
11/12/2018