CMPE 382 / ECE 510 Computer Organization & Architecture Chapter 1 - Introduction based on text: Computer Architecture : A Quantitative Approach (Paperback)

CMPE 382 / ECE 510 Computer Organization & Architecture Chapter 1 - Introduction
based on text: Computer Architecture : A Quantitative Approach (Paperback) John L. Hennessy, David A. Patterson Morgan Kaufmann; 4th edition 2006 Many lecture slides are courtesy of or based on the work of Drs. Asanovic, Patterson, Culler and Amaral CS252 S05

Computing Devices Then…
EDSAC, University of Cambridge, UK, 1949 cmpe382/ece510 ch 1 CS252 S05

cmpe382/ece510 ch 1

What is Computer Architecture?
Application Gap too large to bridge in one step (but there are exceptions, e.g. magnetic compass) Physics In its broadest definition, computer architecture is the design of the abstraction layers that allow us to implement information processing applications efficiently using available manufacturing technologies. cmpe382/ece510 ch 1 CS252 S05

Abstraction Layers in Modern Systems
Application Algorithm Original domain of the computer architect (‘50s-’80s) Programming Language Reliability, power, … Parallel computing, security, … Reinvigoration of computer architecture, mid-2000s onward. Operating System/Virtual Machine Domain of recent computer architecture (‘90s) Instruction Set Architecture (ISA) Microarchitecture Gates/Register-Transfer Level (RTL) Circuits Devices Physics cmpe382/ece510 ch 1 CS252 S05

The End of the Uniprocessor Era
Single biggest change in the history of computing systems cmpe382/ece510 ch 1 CS252 S05

Technology Trends (Summary)
Capacity Speed (latency) Logic 2x in 3 years 2x in 3 years DRAM 4x in 3-4 years 2x in 10 years Disk 4x in 2 years 2x in 10 years cmpe382/ece510 ch 1

An old slide on Processor Performance Trends
Microprocessors Minicomputers Mainframes Supercomputers Year 0.1 1 10 100 1000 1965 1970 1975 1980 1985 1990 1995 2000 cmpe382/ece510 ch 1

Uniprocessor Performance
From Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4th edition, October, 2006 VAX : 25%/year 1978 to 1986 RISC + x86: 52%/year 1986 to 2002 RISC + x86: ??%/year 2002 to present cmpe382/ece510 ch 1 CS252 S05

Growth in processor outpaces growth in logic speed
What else is in a computer architect’s bag of tricks?

Conventional Wisdom in Computer Architecture
Old Conventional Wisdom: Power is free, Transistors expensive New Conventional Wisdom: “Power wall” Power expensive, Transistors free (Can put more on chip than can afford to turn on) Old CW: Sufficient increasing Instruction-Level Parallelism via compilers, innovation (Out-of-order, speculation, VLIW, …) New CW: “ILP wall” law of diminishing returns on more HW for ILP Old CW: Multiplies are slow, Memory access is fast New CW: “Memory wall” Memory slow, multiplies fast (200 clock cycles to DRAM memory, 4 clocks for multiply) Old CW: Uniprocessor performance 2X / 1.5 yrs New CW: Power Wall + ILP Wall + Memory Wall = Brick Wall Uniprocessor performance now 2X / 5(?) yrs  Sea change in chip design: multiple “cores” (2X processors per chip / ~ 2 years) More, simpler processors are more power efficient cmpe382/ece510 ch 1 CS252 S05

Processor is the new transistor?
Change in Chip Design Intel 4004 (1971): 4-bit processor, 2312 transistors, 0.4 MHz, 10 micron PMOS, 11 mm2 chip RISC II (1983): 32-bit, 5 stage pipeline, 40,760 transistors, 3 MHz, 3 micron NMOS, 60 mm2 chip 125 mm2 chip = RISC II+FPU+Icache+Dcache RISC II shrinks to ~ 0.02 mm2 at 65 nm Size of 4 transistors in on 4004 Processor is the new transistor? cmpe382/ece510 ch 1 CS252 S05

Déjà vu all over again? Multiprocessors imminent in 1970s, ‘80s, ‘90s, … “… today’s processors … are nearing an impasse as technologies approach the speed of light..” David Mitchell, The Transputer: The Time Is Now (1989) Transputer was premature  Custom multiprocessors tried to beat uniprocessors  Procrastination rewarded: 2X seq. perf. / 1.5 years “We are dedicating all of our future product development to multicore designs. … This is a sea change in computing” Paul Otellini, President, Intel (2004) Difference is all microprocessor companies have switched to multiprocessors (AMD, Intel, IBM, Sun; all new Apples 2+ CPUs)  Procrastination penalized: 2X sequential perf. / 5 yrs  Biggest programming challenge: from 1 to 2 CPUs cmpe382/ece510 ch 1 CS252 S05

Problems with Change Algorithms, Programming Languages, Compilers, Operating Systems, Architectures, Libraries, … not ready to supply Thread-Level Parallelism or Data-Level Parallelism for 1000 CPUs / chip, Architectures not ready for 1000 CPUs / chip Unlike Instruction-Level Parallelism, cannot be solved by computer architects and compiler writers alone, but also cannot be solved without participation of architects 4th Edition of textbook Computer Architecture: A Quantitative Approach explores shift from Instruction-Level Parallelism to Thread-Level Parallelism / Data-Level Parallelism cmpe382/ece510 ch 1 CS252 S05

Instruction Set Architecture: Critical Interface
software instruction set hardware Properties of a good abstraction Lasts through many generations (portability) Used in many different ways (generality) Provides convenient functionality to higher levels Permits an efficient implementation at lower levels cmpe382/ece510 ch 1 CS252 S05

Instruction Set Architecture
“... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.” – Amdahl, Blaauw, and Brooks, 1964 SOFTWARE -- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions cmpe382/ece510 ch 1 CS252 S05

Example: MIPS r0 Programmable storage r1 Data types ? 2^32 x bytes °
Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0=0) 32 x 32-bit FP regs (paired DP) HI, LO, PC Data types ? Format ? Addressing Modes? PC lo hi Arithmetic logical Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR Control J, JAL, JR, JALR BEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL 32-bit instructions on word boundary cmpe382/ece510 ch 1 CS252 S05

ISA vs. Computer Architecture
Old definition of computer architecture = instruction set design Other aspects of computer design called implementation Insinuates implementation is uninteresting or less challenging Our view is computer architecture >> ISA Architect’s job much more than instruction set design; technical hurdles today more challenging than those in instruction set design Since instruction set design not where action is, some conclude computer architecture (using old definition) is not where action is We disagree on conclusion Agree that ISA not where action is (ISA in CA:AQA 4/e appendix) cmpe382/ece510 ch 1 CS252 S05

Computer Architecture is an Integrated Approach
What really matters is the functioning of the complete system hardware, runtime system, compiler, operating system, and application In networking, this is called the “End to End argument” Computer architecture is not just about transistors, individual instructions, or particular implementations E.g., Original RISC projects replaced complex instructions with a compiler + simple instructions cmpe382/ece510 ch 1 CS252 S05

Computer Architecture is Design and Analysis
Architecture is an iterative process: Searching the space of possible designs At all levels of computer systems Creativity Cost / Performance Analysis Good Ideas Mediocre Ideas Bad Ideas cmpe382/ece510 ch 1 CS252 S05

What Computer Architecture brings to Table
Other fields often borrow ideas from architecture Quantitative Principles of Design Take Advantage of Parallelism Principle of Locality Focus on the Common Case Amdahl’s Law The Processor Performance Equation Careful, quantitative comparisons Define, quantity, and summarize relative performance Define and quantity relative cost Define and quantity dependability Define and quantity power Culture of anticipating and exploiting advances in technology Culture of well-defined interfaces that are carefully implemented and thoroughly checked cmpe382/ece510 ch 1 CS252 S05

1) Taking Advantage of Parallelism
Increasing throughput of server computer via multiple processors or multiple disks Detailed HW design Carry lookahead adders uses parallelism to speed up computing sums from linear to logarithmic in number of bits per operand Multiple memory banks searched in parallel in set-associative caches Pipelining: overlap instruction execution to reduce the total time to complete an instruction sequence. Not every instruction depends on immediate predecessor  executing instructions completely/partially in parallel possible Classic 5-stage pipeline: 1) Instruction Fetch (Ifetch), 2) Register Read (Reg), 3) Execute (ALU), 4) Data Memory Access (Dmem), 5) Register Write (Reg) cmpe382/ece510 ch 1 CS252 S05

Pipelined Instruction Execution
Time (clock cycles) Reg ALU DMem Ifetch Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7 Cycle 5 cmpe382/ece510 ch 1 CS252 S05

What’s a Clock Cycle? Old days: 10+ levels of gates
Latch or register combinational logic Old days: 10+ levels of gates Today: determined by numerous time-of-flight issues + gate delays clock propagation, wire lengths, repeaters 16-24 FO4 common (roughly 8-12 classic gate delays) cmpe382/ece510 ch 1 CS252 S05

Limits to pipelining Hazards prevent next instruction from executing during its designated clock cycle Structural hazards: attempt to use the same hardware to do two different things at once Data hazards: Instruction depends on result of prior instruction still in the pipeline Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). Time (clock cycles) I n s t r. O r d e Reg ALU DMem Ifetch Reg ALU DMem Ifetch Reg ALU DMem Ifetch Reg ALU DMem Ifetch cmpe382/ece510 ch 1 CS252 S05

2) The Principle of Locality
Program access a relatively small portion of the address space at any instant of time. Two Different Types of Locality: Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon (e.g., loops, reuse) Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon (e.g., straight-line code, array access) Last 30 years, HW relied on locality for memory perf. The principle of locality states that programs access a relatively small portion of the address space at any instant of time. This is kind of like in real life, we all have a lot of friends. But at any given time most of us can only keep in touch with a small group of them. There are two different types of locality: Temporal and Spatial. Temporal locality is the locality in time which says if an item is referenced, it will tend to be referenced again soon. This is like saying if you just talk to one of your friends, it is likely that you will talk to him or her again soon. This makes sense. For example, if you just have lunch with a friend, you may say, let’s go to the ball game this Sunday. So you will talk to him again soon. Spatial locality is the locality in space. It says if an item is referenced, items whose addresses are close by tend to be referenced soon. Once again, using our analogy. We can usually divide our friends into groups. Like friends from high school, friends from work, friends from home. Let’s say you just talk to one of your friends from high school and she may say something like: “So did you hear so and so just won the lottery.” You probably will say NO, I better give him a call and find out more. So this is an example of spatial locality. You just talked to a friend from your high school days. As a result, you end up talking to another high school friend. Or at least in this case, you hope he still remember you are his friend. +3 = 10 min. (X:50) P $ MEM cmpe382/ece510 ch 1 CS252 S05

Levels of the Memory Hierarchy
Capacity Access Time Cost Staging Xfer Unit CPU Registers 100s Bytes 300 – 500 ps ( ns) Upper Level Registers prog./compiler 1-8 bytes Instr. Operands faster L1 Cache L1 and L2 Cache 10s-100s K Bytes ~1 ns - ~10 ns $1000s/ GByte cache cntl 32-64 bytes Blocks L2 Cache cache cntl bytes Blocks Main Memory G Bytes 80ns- 200ns ~ $100/ GByte Memory OS 4K-8K bytes Pages Disk 10s T Bytes, 10 ms (10,000,000 ns) ~ $1 / GByte Disk user/operator Mbytes Files Larger Tape infinite sec-min ~$1 / GByte Tape Lower Level cmpe382/ece510 ch 1 CS252 S05

3) Focus on the Common Case
Common sense guides computer design Since we’re engineering, common sense is valuable In making a design trade-off, favor the frequent case over the infrequent case E.g., Instruction fetch and decode unit used more frequently than multiplier, so optimize it 1st E.g., If database server has 50 disks / processor, storage dependability dominates system dependability, so optimize it 1st Frequent case is often simpler and can be done faster than the infrequent case E.g., overflow is rare when adding 2 numbers, so improve performance by optimizing more common case of no overflow May slow down overflow, but overall performance improved by optimizing for the normal case What is frequent case and how much performance improved by making case faster => Amdahl’s Law cmpe382/ece510 ch 1 CS252 S05

Which is faster? Time to run the task (ExTime)
Plane Boeing 747 Concorde Speed 610 mph 1350 mph DC to Paris 6.5 hours 3 hours Passengers 470 132 Throughput (pmph) 286,700 178,200 Fastest for 1 person? Which takes less time to transport 470 passengers? Time to run the task (ExTime) Execution time, response time, latency Tasks per day, hour, week, sec, ns … (Performance) Throughput, bandwidth cmpe382/ece510 ch 1 CS252 S05

Definitions Performance is in units of things per sec
bigger is better If we are primarily concerned with response time performance(x) = execution_time(x) " X is n times faster than Y" means Performance(X) Execution_time(Y) n = = Performance(Y) Execution_time(X) cmpe382/ece510 ch 1

Measurement Tools Real Programs, Benchmarks, Traces, Mixes
Hardware: Cost, delay, area, power estimation Simulation (many levels) ISA, RT, Gate, Circuit Queuing Theory Rules of Thumb Fundamental “Laws”/Principles cmpe382/ece510 ch 1 CS252 S05

And now some math

5) Processor performance equation
CPI 5) Processor performance equation “Iron Law of Performance” inst count Cycle time CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle Inst Count CPI Clock Rate Program X Compiler X (X) Inst. Set X X Organization X X Technology X cmpe382/ece510 ch 1 CS252 S05

Cycles Per Instruction
We may separate the contribution of each type of instruction to the execution time defining: Processor pipelining and memory interactions limit the accuracy of this approach, but its a good first guess. For accuracy, it is necessary to simulate the instructions of an entire program with issue, pipeline and memory interactions. cmpe382/ece510 ch 1 CS252 S05

Example: Calculating CPI
Base Machine (Reg / Reg) Op Freq Cycles CPI(i) (% Time) ALU 50% (33%) Load 20% (27%) Store 10% (13%) Branch 20% (27%) 1.5 Typical Mix of instruction types in program cmpe382/ece510 ch 1 CS252 S05

4) Amdahl’s Law Best you could ever hope to do: cmpe382/ece510 ch 1
CS252 S05

Amdahl’s Law example New CPU 10X faster I/O bound server, so 60% time waiting for I/O Apparently, it’s human nature to be attracted by 10X faster, vs. keeping in perspective it’s just 1.6X faster cmpe382/ece510 ch 1 CS252 S05

Metrics of Performance
Application Answers per month Operations per second Programming Language Compiler (millions) of Instructions per second: MIPS (millions) of (FP) operations per second: MFLOP/s ISA Datapath Megabytes per second Control Function Units Cycles per second (clock rate) Transistors Wires Pins cmpe382/ece510 ch 1

Metrics used to Compare Designs
Cost Die cost and system cost Execution Time average and worst-case Latency vs. Throughput Energy and Power Also peak power and peak switching current Reliability Resiliency to electrical noise, part failure Robustness to bad software, operator error Maintainability System administration costs Compatibility Software costs dominate cmpe382/ece510 ch 1 CS252 S05

Architect affects all of these
Cost of Processor Design cost (Non-recurring Engineering Costs, NRE) dominated by engineer-years (~$200K per engineer year) also mask costs (exceeding $1M per spin) Cost of die die area die yield (maturity of manufacturing process, redundancy features) cost/size of wafers die cost ~= f(die area^4) with no redundancy Cost of packaging number of pins (signal + power/ground pins) power dissipation Cost of testing built-in test features? logical complexity of design choice of circuits (minimum clock rates, leakage currents, I/O drivers) Architect affects all of these cmpe382/ece510 ch 1 CS252 S05

System-Level Cost Impacts
Power supply and cooling Support chipset Off-chip SRAM/DRAM/ROM Off-chip peripherals cmpe382/ece510 ch 1 CS252 S05

Summarizing Performance
System Rate (Task 1) Rate (Task 2) A 10 20 B Which system is faster? cmpe382/ece510 ch 1 CS252 S05

… depends who’s selling
System Rate (Task 1) Rate (Task 2) A 10 20 B Average 15 Average throughput System Rate (Task 1) Rate (Task 2) A 0.50 2.00 B 1.00 Average 1.25 Throughput relative to B System Rate (Task 1) Rate (Task 2) A 1.00 B 2.00 0.50 Average 1.25 Throughput relative to A cmpe382/ece510 ch 1 CS252 S05

How to Mislead with Performance Reports
Select pieces of workload that work well on your design, ignore others Use unrealistic data set sizes for application (too big or too small) Report throughput numbers for a latency benchmark Report latency numbers for a throughput benchmark Report performance on a kernel and claim it represents an entire application Use 16-bit fixed-point arithmetic (because it’s fastest on your system) even though application requires 64-bit floating-point arithmetic Use a less efficient algorithm on the competing machine Report speedup for an inefficient algorithm (bubblesort) Compare hand-optimized assembly code with unoptimized C code Compare your design using next year’s technology against competitor’s year old design (1% performance improvement per week) Ignore the relative cost of the systems being compared Report averages and not individual results Report speedup over unspecified base system, not absolute times Report efficiency not absolute times Report MFLOPS not absolute times (use inefficient algorithm) [ David Bailey “Twelve ways to fool the masses when giving performance results for parallel supercomputers” ] cmpe382/ece510 ch 1 CS252 S05

Power and Energy Energy to complete operation (Joules)
Corresponds approximately to battery life (Battery energy capacity actually depends on rate of discharge) Peak power dissipation (Watts = Joules/second) Affects packaging (power and ground pins, thermal design) di/dt, peak change in supply current (Amps/second) Affects power supply noise (power and ground pins, decoupling capacitors) cmpe382/ece510 ch 1 CS252 S05

SPEC: System Performance Evaluation Cooperative
First Round 1989 10 programs yielding a single number (“SPECmarks”) Second Round 1992 SPECInt92 (6 integer programs) and SPECfp92 (14 floating point programs) Compiler Flags unlimited. March 93 of DEC 4000 Model 610: spice: unix.c:/def=(sysv,has_bcopy,”bcopy(a,b,c)= memcpy(b,a,c)” wave5: /ali=(all,dcom=nat)/ag=a/ur=4/ur=200 nasa7: /norecu/ag=a/ur=4/ur2=200/lc=blas Third Round 1995 new set of programs: SPECint95 (8 integer programs) and SPECfp95 (10 floating point) “benchmarks useful for 3 years” Single flag setting for all programs: SPECint_base95, SPECfp_base95 cmpe382/ece510 ch 1

SPEC CPU2000 Suite Larger benchmarks, data won’t fit in newer larger caches observed difference between peak&base less Benchmark specific tuning more difficult (contrast kernels, synthetic benchmarks) 12 previous benchmarks dropped more at Goal of all SPEC benchmarks: direct energy towards making real applications faster cmpe382/ece510 ch 1

SPEC CPU2000 SPEC CPU2000 suite includes applications from the following areas: AI game theory compilers interpreters data compression databases weather prediction fluid dynamics physics chemistry image processing cmpe382/ece510 ch 1

Other Benchmark Suites
MSWindows/Desktop [Ziff Davis] Business Winstone, CC Winstone, Winbench SPEC CPU + SPECviewperf, SPECapc Transaction processing throughput with acceptable response time TPC-C (database update e.g. ATM) TPC-H, TPC-R decision support TPC-W business web transactions EEMBC embedded benchmarks automotive, consumer, network, office, telco (hand written assembler code allowed) cmpe382/ece510 ch 1

How to Summarize Performance
Arithmetic mean (weighted arithmetic mean) tracks execution time: (Ti)/n or (Wi*Ti) Harmonic mean (weighted harmonic mean) of rates (e.g., MFLOPS) tracks execution time: n/(1/Ri) or 1/(Wi/Ri) Normalized execution time is handy for scaling performance (e.g., X times faster than SPARCstation 10) But do not take the arithmetic mean of normalized execution time, use the geometric mean: nRi cmpe382/ece510 ch 1

The Best Benchmarks? Time the execution of the application you will be running, weighted in accordance to your usage Else, use someone else’s measured runtimes (benchmark suite), weighted in accordance to your usage Else, use benchmark suite with geometric mean summary Else kernels (application fragments), toy benchmarks, synthetic benchmarks (yuk) cmpe382/ece510 ch 1

Performance Evaluation
“For better or worse, benchmarks shape a field” Good products created when have: Good benchmarks Good ways to summarize performance Given sales is a function in part of performance relative to competition, investment in improving product as reported by performance summary If benchmarks/summary inadequate, then choose between improving product for real programs vs. improving product to get more sales; Sales almost always wins! Execution time is the measure of computer performance! cmpe382/ece510 ch 1

And in conclusion … Computer Architecture >> instruction sets
Computer Architecture skill sets are different 5 Quantitative principles of design Quantitative approach to design Solid interfaces that really work Technology tracking and anticipation learn new skills, transition to research Computer Architecture at the crossroads from sequential to parallel computing Salvation requires innovation in many fields, including computer architecture Read Chapter 1, then Appendices B&A cmpe382/ece510 ch 1 CS252 S05

CMPE 382 / ECE 510 Computer Organization & Architecture Chapter 1 - Introduction based on text: Computer Architecture : A Quantitative Approach (Paperback)

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CMPE 382 / ECE 510 Computer Organization & Architecture Chapter 1 - Introduction based on text: Computer Architecture : A Quantitative Approach (Paperback)

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