1. Microprocessors course
In The Name Of God
Microcontroller 8051
Section 1
Microprocessors course
Dr. S.O.Fatemi
By: Mahdi Hassanpour
Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

2. Contents: Introduction Block Diagram and Pin Description of the 8051
Registers
Some Simple Instructions
Structure of Assembly language and Running an 8051 program
Memory mapping in 8051
8051 Flag bits and the PSW register
Addressing Modes
16-bit, BCD and Signed Arithmetic in 8051
Stack in the 8051
LOOP and JUMP Instructions
CALL Instructions
I/O Port Programming
Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

3. Introduction General-purpose microprocessor CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example：Intel’s x86, Motorola’s 680x0
Many chips on mother’s board
Data Bus
CPU
General-Purpose Micro-processor
Serial COM Port
I/O Port
Intel’s x86: 8086,8088,80386,80486, Pentium
Motorola’s 680x0: 68000, 68010, 68020,68030,6040
RAM
ROM
Timer
Address Bus
General-Purpose Microprocessor System
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Mahdi Hassanpour

4. Microcontroller : A single chip A smaller computer
On-chip RAM, ROM, I/O ports...
Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
CPU
RAM
ROM
A single chip
Serial COM Port
I/O Port
Timer
Microcontroller
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Mahdi Hassanpour

5. Microprocessor vs. Microcontroller
CPU is stand-alone, RAM, ROM, I/O, timer are separate
designer can decide on the amount of ROM, RAM and I/O ports.
expansive
versatility
general-purpose
Microcontroller
CPU, RAM, ROM, I/O and timer are all on a single chip
fix amount of on-chip ROM, RAM, I/O ports
for applications in which cost, power and space are critical
single-purpose
versatility 多用途的: any number of applications for PC
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Mahdi Hassanpour

6. Embedded System
Embedded system means the processor is embedded into that application.
An embedded product uses a microprocessor or microcontroller to do one task only.
In an embedded system, there is only one application software that is typically burned into ROM.
Example：printer, keyboard, video game player
processor 整合到整個系統中, 你只看到此系統的外觀, 應用, 感覺不到有 processor 在其中.
Embedded system 通常只有一項應用, 而 PC 有許多 applications (game, accounting, fax, mail...)
A printer is an example of embedded system since the processor inside it performs one task only.
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Mahdi Hassanpour

7. Three criteria in Choosing a Microcontroller
meeting the computing needs of the task efficiently and cost effectively
speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption
easy to upgrade
cost per unit
availability of software development tools
assemblers, debuggers, C compilers, emulator, simulator, technical support
wide availability and reliable sources of the microcontrollers.
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Mahdi Hassanpour

8. Block Diagram External interrupts On-chip ROM for program code
Timer/Counter
Interrupt Control
On-chip RAM
Timer 1
Counter Inputs
Timer 0
CPU
Serial Port
Bus Control
4 I/O Ports
OSC
P0 P1 P2 P3
TxD RxD
Address/Data
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Mahdi Hassanpour

9. Comparison of the 8051 Family Members
Feature
ROM (program space in bytes) 4K K K
RAM (bytes)
Timers
I/O pins
Serial port
Interrupt sources
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Mahdi Hassanpour

10. Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

11. Pin Description of the 8051 8051 (8031) PDIP/Cerdip  1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
GND
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051
(8031) 
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Mahdi Hassanpour

12. Pins of 8051（1/4）
Vcc（pin 40）：
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND（pin 20）：ground
XTAL1 and XTAL2（pins 19,18）：
These 2 pins provide external clock.
Way 1：using a quartz crystal oscillator 
Way 2：using a TTL oscillator 
Example 4-1 shows the relationship between XTAL and the machine cycle. 
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Mahdi Hassanpour

13. Pins of 8051（2/4） RST（pin 9）：reset
It is an input pin and is active high（normally low）.
The high pulse must be high at least 2 machine cycles.
It is a power-on reset.
Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost.
Reset values of some 8051 registers 
Way 1：Power-on reset circuit 
Way 2：Power-on reset with debounce 
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Mahdi Hassanpour

14. Pins of 8051（3/4） /EA（pin 31）：external access
There is no on-chip ROM in 8031 and
The /EA pin is connected to GND to indicate the code is stored externally.
/PSEN ＆ ALE are used for external ROM.
For 8051, /EA pin is connected to Vcc.
“/” means active low.
/PSEN（pin 29）：program store enable
This is an output pin and is connected to the OE pin of the ROM.
See Chapter 14.
Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

15. Pins of 8051（4/4） ALE（pin 30）：address latch enable
It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
I/O port pins
The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional.
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Mahdi Hassanpour

16. Figure 4-2 (a). XTAL Connection to 8051
Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin. C2
30pF C1
XTAL2
XTAL1
GND 
Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

17. Figure 4-2 (b). XTAL Connection to an External Clock Source
Using a TTL oscillator
XTAL2 is unconnected. NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
GND 
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Mahdi Hassanpour

18.  Example : Find the machine cycle for (a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
Solution:
(a) MHz / 12 = kHz;
machine cycle = 1 / kHz = s
(b) 16 MHz / 12 = MHz;
machine cycle = 1 / MHz = 0.75 s 
Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

19. RESET Value of Some 8051 Registers:PC
0000
ACC
0000 B
0000
PSW
0000 SP
0007
DPTR
0000
RAM are all zero. 
Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

20. Figure 4-3 (a). Power-On RESET Circuit
Vcc +
10 uF 31
EA/VPP X1
30 pF 19
MHz
8.2 K X2 18
30 pF
RST 9 
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Mahdi Hassanpour

21. Figure 4-3 (b). Power-On RESET with Debounce
Vcc 31
EA/VPP X1
10 uF
30 pF X2
RST 9
8.2 K 
Wednesday, November 07, 2018Wednesday, November 07, 2018
Mahdi Hassanpour

22. Pins of I/O Port The 8051 has four I/O ports
Port 0 （pins 32-39）：P0（P0.0～P0.7）
Port 1（pins 1-8） ：P1（P1.0～P1.7）
Port 2（pins 21-28）：P2（P2.0～P2.7）
Port 3（pins 10-17）：P3（P3.0～P3.7）
Each port has 8 pins.
Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X
Ex：P0.0 is the bit 0（LSB）of P0
Ex：P0.7 is the bit 7（MSB）of P0
These 8 bits form a byte.
Each port can be used as input or output (bi-direction).
Program is to read data from P0 and then send data to P1 
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Mahdi Hassanpour

23. Some 8-bitt Registers of the 8051A B R0 R1 R3 R4 R2 R5 R7 R6
DPH
DPL PC
DPTR
Some bit Register
Some 8-bitt Registers of the 8051
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Mahdi Hassanpour

24. Some Simple Instructions
MOV dest,source ; dest = source
MOV A,#72H ;A=72H
MOV A, #’r’ ;A=‘r’ OR 72H
MOV R4,#62H ;R4=62H
MOV B,0F9H ;B=the content of F9’th byte of RAM
MOV DPTR,#7634H
MOV DPL,#34H
MOV DPH,#76H
MOV P1,A ;mov A to port 1
Note 1:
MOV A,#72H ≠ MOV A,72H
After instruction “MOV A,72H ” the content of 72’th byte of RAM will replace in Accumulator.
MOV AL,72H MOV A,#72H
MOV AL,’r’ MOV A,#’r’
MOV BX,72H
MOV AL,[BX] MOV A,72H
Note 2:
MOV A,R3 ≡ MOV A,3
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25. ADD A, Source ;A=A+SOURCE
ADD A,#6 ;A=A+6
ADD A,R6 ;A=A+R6
ADD A,6 ;A=A+[6] or A=A+R6
ADD A,0F3H ;A=A+[0F3H]
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26. SETB bit ; bit=1 CLR bit ; bit=0 SETB C ; CY=1
SETB P0.0 ;bit 0 from port 0 =1
SETB P3.7 ;bit 7 from port 3 =1
SETB ACC.2 ;bit 2 from ACCUMULATOR =1
SETB 05 ;set high D5 of RAM loc. 20h
Note:
CLR instruction is as same as SETB
i.e:
CLR C ;CY=0
But following instruction is only for CLR:
CLR A ;A=0
Bit Addressable
Page 359,360
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Mahdi Hassanpour

27. SUBB A,source ;A=A-source-CY
SETB C ;CY=1
SUBB A,R5 ;A=A-R5-1
ADC A,source ;A=A+source+CY
ADC A,R5 ;A=A+R5+1
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28. DEC byte ;byte=byte-1 INC byte ;byte=byte+1 CPL A ;1’s complement
INC R7
DEC A
DEC 40H ; [40]=[40]-1
CPL A ;1’s complement
Example:
MOV A,#55H ;A= B
L01: CPL A
MOV P1,A
ACALL DELAY
SJMP L01
NOP & RET & RETI
All are like 8086 instructions.
 CALL
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29. ANL - ORL - XRL EXAMPLE: MOV R5,#89H ANL R5,#08H RR – RL – RRC – RLC A
RR A
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Mahdi Hassanpour

30. Structure of Assembly language and Running an 8051 program
EDITOR
PROGRAM
ASSEMBLER
LINKER OH
Myfile.asm
Myfile.obj
Other obj file
Myfile.lst
Myfile.abs
Myfile.hex
ORG 0H
MOV R5,#25H
MOV R7,#34H
MOV A,#0
ADD A,R5
ADD A,#12H
HERE: SJMP HERE
END
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Mahdi Hassanpour

31. Memory mapping in 8051 ROM memory map in 8051 family 4k 8k 32k
0000H
0FFFH
1FFFH
7FFFH
8751
AT89C51
8752
AT89C52 4k 8k
32k DS
from Atmel Corporation
from Dallas Semiconductor
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Mahdi Hassanpour

32. RAM memory space allocation in the 8051
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(Stack) Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
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Mahdi Hassanpour

33. 8051 Flag bits and the PSW registerCY AC F0
RS1 OV
RS0 P --
CY PSW.7 Carry flag
AC PSW.6 Auxiliary carry flag
-- PSW.5 Available to the user for general purpose
RS1 PSW.4 Register Bank selector bit 1
RS0 PSW.3 Register Bank selector bit 0
OV PSW.2 Overflow flag
-- PSW.1 User define bit
P PSW.0 Parity flag Set/Reset odd/even parity
RS1 RS0 Register Bank Address
H-07H
H-0FH
H-17H
H-1FH
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34. Instructions that Affect Flag Bits:
Note: X can be 0 or 1
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35. Example: MOV A,#88H ADD A,#93H 88 10001000 +93 +10010011
11B
CY=1 AC=0 P=0
Example:
MOV A,#9CH
ADD A,#64H 9C
CY=1 AC=1 P=0
Example:
MOV A,#38H
ADD A,#2FH
+2F
CY=0 AC=1 P=1
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36. Addressing Modes Immediate Register Direct Register Indirect Indexed
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37. Immediate Addressing Mode
MOV A,#65H
MOV A,#’A’
MOV R6,#65H
MOV DPTR,#2343H
MOV P1,#65H
Example :
Num EQU 30 …
MOV R0,Num
MOV DPTR,#data1
ORG 100H
data1: db “IRAN”
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38. Register Addressing Mode
MOV Rn, A ;n=0,..,7
ADD A, Rn
MOV DPL, R6
MOV DPTR, A
MOV Rm, Rn
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39. Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode, it is most often used to access RAM loc. 30 – 7FH.
MOV R0, 40H
MOV 56H, A
MOV A, 4 ; ≡ MOV A, R4
MOV 6, 2 ; copy R2 to R6
; MOV R6,R2 is invalid !
SFR register and their address
MOV 0E0H, #66H ; ≡ MOV A,#66H
MOV 0F0H, R2 ; ≡ MOV B, R2
MOV 80H,A ; ≡ MOV P1,A
Bit Addressable
Page 359,360
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Mahdi Hassanpour

40. Register Indirect Addressing Mode
In this mode, register is used as a pointer to the data.
MOV ; move content of RAM loc.Where address is held by Ri into A
( i=0 or 1 )
MOV @R1,B
In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB insructions.
Example:
Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h.
Solution:
MOV R0,37h ; source pointer
MOV R1,59h ; dest pointer
MOV R2,10 ; counter
L1: MOV
MOV @R1,A
INC R0
INC R1
DJNZ R2,L1
jump
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Mahdi Hassanpour

41. Indexed Addressing Mode And On-Chip ROM Access
This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051
MOVC
A= content of address A +DPTR from ROM
Note:
Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The “C” means code.
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42. ;------------------------------------- ORG 250H MYDATA: DB “Hello”,0
Example:
Assuming that ROM space starting at 250h contains “Hello.”, write a program to transfer the bytes into RAM locations starting at 40h.
Solution:
ORG 0
MOV DPTR,#MYDATA
MOV R0,#40H
L1: CLR A
MOVC
JZ L2
MOV @R0,A
INC DPTR
INC R0
SJMP L1
L2: SJMP L2 ;
ORG 250H
MYDATA: DB “Hello”,0
END
Notice the NULL character ,0, as end of string and how we use the JZ instruction to detect that.
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43. ;---------------------------------------------------- ORG 300H
Example:
Write a program to get the x value from P1 and send x2 to P2, continuously .
Solution:
ORG 0
MOV DPTR, #TAB1
MOV A,#0FFH
MOV P1,A
L01:
MOV A,P1
MOVC
MOV P2,A
SJMP L01 ;
ORG 300H
TAB1: DB 0,1,4,9,16,25,36,49,64,81
END
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44. 16-bit, BCD and Signed Arithmetic in 8051
Exercise:
Write a program to add n 16-bit number. Get n from port 1. And sent Sum to LCD
a) in hex
b) in decimal
Write a program to subtract P1 from P0 and send result to LCD
(Assume that “ACAL DISP” display A to LCD )
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45. MUL & DIV MUL AB ;B|A = A*B MOV A,#25H MOV B,#65H MUL AB ;25H*65H=0E99
;B=0EH, A=99H
MUL AB ;A = A/B, B = A mod B
MOV A,#25
MOV B,#10
MUL AB ;A=2, B=5
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Mahdi Hassanpour

46. Stack in the 8051
The register used to access the stack is called SP (stack pointer) register.
The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(Stack) Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
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47. Example: MOV R6,#25H MOV R1,#12H MOV R4,#0F3H PUSH 6 PUSH 1 PUSH 4
0BH
0AH
09H
08H
Start SP=07H 25
0BH
0AH
09H
08H
SP=08H 12 25
0BH
0AH
09H
08H
SP=09H F3 12 25
0BH
0AH
09H
08H
SP=08H
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48. LOOP and JUMP Instructions
DJNZ:
Write a program to clear ACC, then
add 3 to the accumulator ten time
Solution:
MOV A,#0;
MOV R2,#10
AGAIN: ADD A,#03
DJNZ R2,AGAING ;repeat until R2=0 (10 times)
MOV R5,A
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49. Other conditional jumps :JZ
Jump if A=0
JNZ
Jump if A/=0
DJNZ
Decrement and jump if A/=0
CJNE A,byte
Jump if A/=byte
CJNE reg,#data
Jump if byte/=#data JC
Jump if CY=1
JNC
Jump if CY=0 JB
Jump if bit=1
JNB
Jump if bit=0
JBC
Jump if bit=1 and clear bit
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50. SJMP and LJMP: LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction in which the first byte is the opcode, and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location from 0000 to FFFFH.
SJMP(short jump)
In this 2-byte instruction. The first byte is the opcode and the second byte is the relative address of the target location. The relative address range of 00-FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.
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51. CJNE , JNC Exercise: Write a program that compare R0,R1.
If R0>R1 then send 1 to port 2,
else if R0<R1 then send 0FFh to port 2,
else send 0 to port 2.
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52. CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine.
LCALL(long call)
In this 3-byte instruction, the first byte is the opcode an the second and third bytes are used for the address of target subroutine. Therefore, LCALL can be used to call subroutines located anywhere within the 64K byte address space of the 8051.
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53. ACALL (absolute call)
ACALL is 2-byte instruction in contrast to LCALL, which is 13 bytes. Since ACALL is a 2-byte instruction, the target address of the subroutine must be within 2K bytes address because only 11 bits of the 2 bytes are used for the address. There is no difference between ACALL and LCALL in terms of saving the program counter on the stack or the function of the RET instruction. The only difference is that the target address for LCALL can be anywhere within the 64K byte address space of the 8051 while the target address of ACALL must be within a 2K-byte range.
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54. I/O Port Programming Port 1（pins 1-8） Port 1 is denoted by P1.
Port 1 is denoted by P1.
P1.0 ~ P1.7
We use P1 as examples to show the operations on ports.
P1 as an output port (i.e., write CPU data to the external pin)
P1 as an input port (i.e., read pin data into CPU bus)
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55. A Pin of Port 1 P0.x 8051 IC Read latch Vcc TB2 Load(L1) P1.X pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB1
TB2
P0.x
8051 IC
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Mahdi Hassanpour

56. Hardware Structure of I/O Pin
Each pin of I/O ports
Internal CPU bus：communicate with CPU
A D latch store the value of this pin
D latch is controlled by “Write to latch”
Write to latch＝1：write data into the D latch
2 Tri-state buffer：
TB1: controlled by “Read pin”
Read pin＝1：really read the data present at the pin
TB2: controlled by “Read latch”
Read latch＝1：read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close
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57. Tri-state Buffer  Output Input Tri-state control (active high) L L H
Low
Highimpedance (open-circuit) H H 
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58. Writing “1” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. output pin is Vcc
1. write a 1 to the pin 1
output 1
TB1
8051 IC
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59. Writing “0” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. output pin is ground
1. write a 0 to the pin
output 0 1
TB1
8051 IC
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Mahdi Hassanpour

60. Port 1 as Output（Write to a Port）
Send data to Port 1：
MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK
Let P1 toggle.
You can write to P1 directly.
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61. Reading Input v.s. Port Latch
When reading ports, there are two possibilities：
Read the status of the input pin. （from external pin value）
MOV A, PX
JNB P2.1, TARGET ; jump if P2.1 is not set
JB P2.1, TARGET ; jump if P2.1 is set
Figures C-11, C-12
Read the internal latch of the output port.
ANL P1, A ; P1 ← P1 AND A
ORL P1, A ; P1 ← P1 OR A
INC P ; increase P1
Figure C-17
Table C-6 Read-Modify-Write Instruction (or Table 8-5)
See Section 8.3
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62. Reading “High” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
2. MOV A,P1
external pin=High
TB2
write a 1 to the pin MOV P1,#0FFH 1 1
TB1
3. Read pin=1 Read latch=0 Write to latch=1
8051 IC
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63. Reading “Low” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
2. MOV A,P1
external pin=Low
TB2
write a 1 to the pin
MOV P1,#0FFH 1
TB1
3. Read pin=1 Read latch=0 Write to latch=1
8051 IC
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64. Port 1 as Input（Read from Port）
In order to make P1 an input, the port must be programmed by writing 1 to all the bit.
MOV A,#0FFH ;A= B
MOV P1,A ;make P1 an input port
BACK: MOV A,P ;get data from P0
MOV P2,A ;send data to P2
SJMP BACK
To be an input port, P0, P1, P2 and P3 have similar methods.
Program is to read data from P0 and then send data to P1
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65. Instructions For Reading an Input Port
Following are instructions for reading external pins of ports:
Mnemonics
Examples
Description
MOV A,PX
MOV A,P2
Bring into A the data at P2 pins
JNB PX.Y,..
JNB P2.1,TARGET
Jump if pin P2.1 is low
JB PX.Y,..
JB P1.3,TARGET
Jump if pin P1.3 is high
MOV C,PX.Y
MOV C,P2.4
Copy status of pin P2.4 to CY
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66. Reading Latch Exclusive-or the Port 1： MOV P1,#55H ;P1=01010101
ORL P1,#0F0H ;P1=
1. The read latch activates TB2 and bring the data from the Q latch into CPU.
Read P1.0=0
2. CPU performs an operation.
This data is ORed with bit 1 of register A. Get 1.
3. The latch is modified.
D latch of P1.0 has value 1.
4. The result is written to the external pin.
External pin (pin 1: P1.0) has value 1.
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67. Reading the Latch D Q Clk Q
1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.X=0 initially)
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. CPU compute P1.X OR 1
4. P1.X=1 1 1
3. write result to latch Read pin= Read latch= Write to latch=1
TB1
8051 IC
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68. Read-modify-write Feature
Read-modify-write Instructions
Table C-6
This features combines 3 actions in a single instruction：
1. CPU reads the latch of the port
2. CPU perform the operation
3. Modifying the latch
4. Writing to the pin
Note that 8 pins of P1 work independently.
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69. Port 1 as Input（Read from latch）
Exclusive-or the Port 1：
MOV P1,#55H ;P1=
AGAIN: XOR P1,#0FFH ;complement
ACALL DELAY
SJMP AGAIN
Note that the XOR of 55H and FFH gives AAH.
XOR of AAH and FFH gives 55H.
The instruction read the data in the latch (not from the pin).
The instruction result will put into the latch and the pin.
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70. Read-Modify-Write Instructions
Mnemonics
Example
SETB P1.4
SETB PX.Y
CLR P1.3
CLR PX.Y
MOV P1.2,C
MOV PX.Y,C
DJNZ P1,TARGET
DJNZ PX, TARGET
INC P1
INC
CPL P1.2
CPL
JBC P1.1, TARGET
JBC PX.Y, TARGET
XRL P1,A
XRL
ORL P1,A
ORL
ANL P1,A
ANL
DEC P1
DEC
ANL: Latch data AND with A , then save back to latch and write to the external pin
ORL: OR XRL: XOR
JBC: jump to TARGET if bit set and clear bit
CPL: complement
INC: increase DEC: decrease
DJNZ: decrease P1 and jump if P1 not zero
MOV the latch value to carry
CLR: clear bit, SETB: set bit
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71. You are able to answer this Questions:
How to write the data to a pin？
How to read the data from the pin？
Read the value present at the external pin.
Why we need to set the pin first？
Read the value come from the latch（not from the external pin）.
Why the instruction is called read-modify write?
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72. Other Pins P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X. 
However, for a programmer, it is the same to program P0, P1, P2 and P3.
All the ports upon RESET are configured as output.
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73. A Pin of Port 0 P1.x 8051 IC Read latch TB2 P0.X pin Internal CPU bus
D Q
Clk Q
Read latch
Read pin
Write to latch
Internal CPU bus M1
P0.X pin
P1.X
TB1
TB2
P1.x
8051 IC
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74. Port 0（pins 32-39） P0 is an open drain.
Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. 
When P0 is used for simple data I/O we must connect it to external pull-up resistors.
Each pin of P0 must be connected externally to a 10K ohm pull-up resistor.
With external pull-up resistors connected upon reset, port 0 is configured as an output port.
Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips.
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75. Port 0 with Pull-Up Resistors
DS5000
8751
8951
Vcc
10 K
Port 0
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76. Dual Role of Port 0
When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions.
8031 is capable of accessing 64K bytes of external memory.
16-bit address：P0 provides both address A0-A7, P2 provides address A8-A15.
Also, P0 provides data lines D0-D7.
When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address.
There is no need for external pull-up resistors as shown in Chapter 14.
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77. 74LS373 8051 ROM 74LS373 ALE P0.0 P0.7 PSEN A0 A7 D0 D7 P2.0 P2.7 A8OE OC EA G
8051
ROM
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78. 2. 74373 latches the address and send to ROM
Reading ROM (1/2)
latches the address and send to ROM
1. Send address to ROM D
74LS373
ALE
P0.0
P0.7
PSEN A0 A7 D0 D7
P2.0
P2.7 A8
A12 OE OC EA G
8051
ROM
Address
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79. Reading ROM (2/2)
latches the address and send to ROM D
74LS373
ALE
P0.0
P0.7
PSEN A0 A7 D0 D7
P2.0
P2.7 A8
A12 OE OC EA G
8051
ROM
Address
3. ROM send the instruction back
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Mahdi Hassanpour

80. ALE Pin
The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
When ALE=0, P0 provides data D0-D7.
When ALE=1, P0 provides address A0-A7.
The reason is to allow P0 to multiplex address and data.
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81. Port 2（pins 21-28）
Port 2 does not need any pull-up resistors since it already has pull-up resistors internally.
In an 8031-based system, P2 are used to provide address A8-A15.
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82. Port 3（pins 10-17）
Port 3 does not need any pull-up resistors since it already has pull-up resistors internally.
Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used.
Port 3 has the additional function of providing signals.
Serial communications signal：RxD, TxD（Chapter 10）
External interrupt：/INT0, /INT1（Chapter 11）
Timer/counter：T0, T1（Chapter 9）
External memory accesses in 8031-based system：/WR, /RD（Chapter 14）
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83. Port 3 Alternate Functions17 RD
P3.7 16 WR
P3.6 15 T1
P3.5 14 T0
P3.4 13
INT1
P3.3 12
INT0
P3.2 11
TxD
P3.1 10
RxD
P3.0
Pin
Function
P3 Bit 
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Mahdi Hassanpour