1. FreePDK45nm Library Validation
Fractal Technologies
FreePDK45nm Library Validation
9/22/2018
Fractal Technologies
Confidential

2. Quality in Design Formats
Formats checked
Formats of FreePDK45nm library checked by Crossfire:
GDSII
LEF
Cell data + technology in one file
Liberty
3 process corners (best, typ, worst)
Verilog
Spice
5 formats (pre_spice (2), spice, post_spice(2))
Custom created parser
Doc (HTML)
Schematic (xpm files)
Additional formats supported
OpenAccess, Cadence, MilkyWay, TLF, PLIB
9/22/2018
Quality in Design Formats

3. Quality in Design Formats
Cell-presence (1)
Using cell-lists provided with library:
Schematics.lst (107 cells)
Fills.lst (6 cells)
Cell presence check
GDSII:
Found all Schematic and Fill cells
LEF
Found all Schematic and Fill cells + Via1 Via2 (from technology)
Liberty
Best: Found all Schematic and Fill cells
Typ: Found all Schematic and Fill cells
Worst: Found all Schematic and Fill cells
Verilog
Spice
Pre (single file + cell based): Found all Schematic and Fill cells
(cell based): Found all Schematic and Fill cells
Post (single file + cell based): Found all Schematic and Fill cells
Docs
All schematic and all Fill cells found
9/22/2018
Quality in Design Formats

4. Quality in Design Formats
Terminals & Pins
Are the same pins defined in all formats?
Used Verilog (Typ) as Golden Reference
Pins of the same name and direction found in:
Liberty (3 corners)
Verilog (3 corners)
Cell Documentation
VDD/VSS terminals are additional in :
LEF
Spice ( 6 formats)
No pins:
GDSII
Golden
Reference
Checked
Format
9/22/2018
Quality in Design Formats

5. Quality in Design Formats
Pin-Labels
Do pins defined in the GR have text labels in the checked formats
Used Veriliog (typ) as golden-reference
All pins from Verilog_typ are found as labels in:
GDSII
Has VDD, VSS labels but Verilog (Typ) has no VDD,VSS pins
All pins have labels in M1 (“11 0”)
All other formats have no text labels (no check needed)
9/22/2018
Quality in Design Formats

6. Quality in Design Formats
Nets
There are no formats with a “net” concept.
Normally these are Cadence-DFII and MilkyWay
9/22/2018
Quality in Design Formats

7. Quality in Design Formats
Layout vs. layout
Checks identity between polygons: layout-vs-layout or abstract-vs-layout
Performs Boolean mask XOR operations
Detailed check example:
“M1 drawing”+”M1 pin” in layout == “M1 net”+”M1 boundary” in abstract
Performed only 1 check for M1
GDSII vs LEF
M1 in GDSII is equal to M1 in LEF
Other formats not relevant (no layout information)
9/22/2018
Quality in Design Formats

8. Quality in Design Formats
LEF cells Check
Checks if LEF cells have the correct size acc. To LEFtech
ALL cells OK
Parsing issues for LEF 5.6
NAMECASESENSITIVE, DIRECTION in VIARULE and turn-via are obsolete in LEF 5.6
9/22/2018
Quality in Design Formats

9. Quality in Design Formats
Routability
Checks if signal-pins can be routed to cell-boundary
Uses fast internal gridded maze router
Users select layers (e.g. M1 only) or special rules (e.g. double-via’s on outputs of high-drive cells)
Technology settings (rules, vias, pitch) read from LEF technology
All pins of all cells routable in M1 and M2
Totally 113 cells with 461 pins
M1 only: 373 pins are not routable
M1 and M2: 312 pins not routable (not on grid)
9/22/2018
Quality in Design Formats

10. Quality in Design Formats
Abutment
All cells checked for self-symmetry and left/right abutment (alignment on cell-boundary) with reference cell (FILLCELL_X1):
layers: M1 CONTACT NWELL PWELL PIMPL NIMPL DIFF M2
Formats: GDSII
No errors found
9/22/2018
Quality in Design Formats

11. Functional Equivalence(1)
Verified functional equivalence between Verilog, SPICE, and Liberty
Checks equivalence of Boolean expressions from different databases
For SPICE, expressions are automatically extracted from the circuit
All Verilog files are equal for the functions
All Liberty files are equal for the functions
Liberty_typ is equal to Verilog_typ
9/22/2018
Quality in Design Formats

12. Functional Equivalence(2)
Verilog_typ/Liberty vs spice
DFFRS_X1 flipflop has non matching QN output with Verilog/Liberty when SN and RN are low and CK 0->1
Verilog UDP table
table
// SN RN nextstate CK NOTIFIER : IQ
? r ? : ? : ;
? r ? : ? : ;
? * ? : 0 : ; // reduce pessimism
? * ? : 1 : ; // reduce pessimism
* ? ? : ? : ; // Ignore all edges on nextstate
? f ? : ? : ; // Ignore non-triggering clock edge
? ? ? ? : ? : ; // RN activated
* ? ? ? : 0 : ; // Cover all transitions on RN
? ? ? : ? : ; // SN activated
* ? ? ? : 1 : ; // Cover all transitions on SN
? ? ? ? * : ? : x; // Any NOTIFIER change
endtable
endprimitive
This means when RN = 0 (and SN = 0) => IQ = 0
9/22/2018
Quality in Design Formats

13. Functional Equivalence(3)
Verilog netlist is:
seq4(IQ, SN, RN, nextstate, CK, NOTIFIER);
and(IQN, i_352, i_353);
not(i_352, IQ);
not(i_353, i_354);
and(i_354, i_355, i_356);
not(i_355, RN);
not(i_356, SN);
buf(Q, IQ);
buf(QN, IQN);
buf(nextstate, D);
This means QN is anded with RN so QN should remain 0 when RN=0
Crossfire output
V:lib0791: 'DFFRS_X1': Equations for terminal 'QN' of format 'pre_spice_1file':
QN=!RN*SN + !RN*CK + SN*CK*!z51 + SN*!CK*z56
z51=!SN + D*!CK + RN*CK*z51
z56=!RN + SN*CK*!z51 + SN*!CK*z56
E:xpr0301: 'DFFRS_X1': Result for output 'QN' is different in '2' situations,
e.g. when 'CK 0->1‘
This means that QN 0->1 when CK 0->1 and RN is 0
9/22/2018
Quality in Design Formats

14. Functional Equivalence(4)
Just to be sure this was simulated with a spice simulator
Plots Q and QN
SN and RN = 0
CK 0->1
Same for:
DFFRS_X2
SDFFRS_X1
SDFFRS_X2
9/22/2018
Quality in Design Formats

15. Functional Equivalence(5)
Advantage of functional equivalence checker
Not simulation based
No test vectors needed.
Completeness
Runs much faster than simulation based.
Seconds instead of hours
9/22/2018
Quality in Design Formats

16. Timing Characterization (1)
Check if all timing arcs exists
Identical timing arcs for all Liberty files
Identical timing arcsfor all Verilog files
Liberty misses many conditional timing arcs compared to verilog_worst, verilog_best
88 cells miss conditional timing arcs in Liberty
All liberty formats have same conditional timing arcs as Verilog_typ.
But verilog file is called “conditional” while data is non conditional?
9/22/2018
Quality in Design Formats

17. Timing Characterization (2)
Missing liberty conditional timing arcs (e.g. XOR2_X2)
Verilog (best): (Line 3218)
if((B == 1'b0)) (A => Z) = (0.1, 0.1);
if((B == 1'b1)) (A => Z) = (0.1, 0.1);
if((A == 1'b1)) (B => Z) = (0.1, 0.1);
if((A == 1'b0)) (B => Z) = (0.1, 0.1);
Liberty (best): (Line 36103)
Has unconditional positive unate nagetive unate
Can negative/positive unate arcs in liberty backanotate to conditionalarcs in Verilog.
We think not if it can this is not really an error
9/22/2018
Quality in Design Formats

18. Timing Characterization (3)
Sanity of timing tables: increasing output delays/slopes for increasing output load and input slope
Verilog files have unit delays 0.1 (not relevant)
Liberty (best,typ,worst) Only Combinational cells (87 cells)
Tol = 0 check for input slope: 623 “errors”
Tol = check for input slope: 199 “errors”
Tol = 0.01 check for input slope: 12 “errors”
Tol = 0.02 check for input slope: 7 “errors” (e.g. INV_X4)
Values (" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ", \
" , , , , , , ");
Smaller Value!
9/22/2018
Quality in Design Formats

19. Timing Characterization (4)
In general: timing table values increase with increasing output loads.
Tol = 0 Check for output cap only: 0 “errors” (all liberty files)
9/22/2018
Quality in Design Formats

20. Custom defined DS – Document
Document format parser was created in an hour (python)
<Cell Name="AND2_X1" CornerName="typical_conditional.lib" LibFile="liberty_typical_conditional.lib.xml">
<Schematic>images/AND2_X1.png</Schematic>
<Navigation>
<Parent Name="Table of Contents" Link="../CornerList.xml"/>
<Next Name="AND2_X2" Link="AND2_X2_typical_conditional.lib.xml"/>
</Navigation>
<GenChars>
<Strength>
1</Strength>
<Type>
Combinational</Type>
<Input>
A1</Input>
A2</Input>
<Output>
ZN</Output>
</GenChars>
<Name>
"AND2_X1"</Name>
if (len(words) >= 2) and (words[0:2] == ['Cell', 'Name']):
cellList = []
cellname = words[2]
print 'CellName: ', cellname
cellList = cellList + [cellname]
outputs = []
if cellname not in CELLLIST:
CELLLIST = CELLLIST + [cellname]
cell[cellname] = library.addCell( cellname )
cv[cellname] = cell[cellname].addCellview ( '' )
if ((l>=2) and
((words[1] == '/Input') or (words[1] == '/Output') or (words[1] == "/InOut"))):
for cellname in cellList:
pin = words[0]
pin_dir = words[1]
print 'Pin: ', pin, pin_dir
DIR = 'UNKNOWN'
if pin_dir == '/Input' : DIR = 'INPUT'
if pin_dir == '/Output' :
DIR = 'OUTPUT'
if not pin in outputs: outputs = [pin] + outputs
if pin_dir == '/InOut' : DIR = 'BIDIRECTIONAL'
term = cv[cellname].addTerminal( pin )
term.setDirection(DIR)
pin = term.addPin()
9/22/2018
Quality in Design Formats

21. Quality in Design Formats
Conclusions
Quality of this library looks pretty good.
FreePDK45nm library contains very few inconsistencies if any
LEF 5.6 obsolete statements
Functional Difference between spice verilog/liberty (S)DFFRS_X1/2
Liberty vs Verilog timing arc issues
Decreasing value entries in the liberty timing tables
Grid-less router needed
9/22/2018
Quality in Design Formats