1. Computer architecture M
P6 Architecture
Computer architecture M

2. PIPELINE IFU1 IFU2 IFU3 8 clocks BUS interface management (in order)
RAT = Register Allocation Table
ROB = ReOrder Buffer
IFU2
IFU3
8 clocks
BUS interface
management
(in order)
DEC1
DEC2
RAT
Renaming
ROB
Variable
number
of clocks
Execution mechanism
(Out-Of-Order)
DIS
Dispatcher
(issues the
u-ops- Risc type ) EX
RET1
Results handling
(in order)
RET2
Between the three main sections compensation queues are inserted. The machine instructions are rotated in order to align them to the decoders. Superpipelined processor (number of stages greater than necessary in order to increase the clock frequency)

3. Behaviour
Instruction extraction from the prefetch queue (a small set of instructions already extracted from the cache )
Instruction decoding and alignment (in order)
Machine instructions translation into RISC m-operations (m-ops) – fixed lenght 118 bit (RISC - in order)
m-operations insertion in the ROB (in order)
Out-of-order m-operations execution for functional modules use - optimization
In order results transfers to the machine registers (commitment)

4. Pipeline stages
IFU1: (Instruction Fetch Stage 1) loads the 2x16=32 bytes buffer (a cache line) directly from L1 cache. While one buffer transfers data to IFU2 the other is loaded by L1
IFU2: (Instruction Fetch Stage 2) detects the instructions boundaries (CISC) for the IFU3. If a branch is detected it is forwarded to the BTB
IFU3: (Instruction Fetch Stage 3) sends the instructions to the appropriate decoders (see later)
DEC1: (Decoder Stage 1) transforms the machine instructions into m-operation (118 bit wide). Up to three IA32 instructions per clock can be processed. For very complex machine instructions a sequencer is used. The m-operations consist of two sources and one destination plus op-code (RISC)
DEC2: (Decoder Stage 2) transfers the m-operations to the decoded instruction queue. Sometimes for very complex instructions (for instnce string instructions) many clocks are requested to complete the operation since the m-instruction queue accepts up to 3 elements per clock. Micro Instruction Sequencer. It includes a second BTB (static – see later)
RAT: (Register AllocationTable) 40 more registers which can be globally allocated

5. Pipeline stages
ROB: loads three m-operations per clock into its buffer. If all m-operations required data are already available (produced by preceding ROB m-operations or already available in the machine registers) and a free slot in the RS queue (Reservation Station of the required functional unit) the m-operation is inserted (here the RS is different from Tomasulo’s. Here in the RS only ready m-operations that is the required operands are already available).
DIS: (DISpatch Stage) if the m-operations in the previous clocks were not inserted into the RS because of lack of the necessary data or slots, inserts the m-operation as soon as the required conditions are met
EX: (EXecution Stage) executes the m-operation. The number of clocks necessary depends on the m-operation. Several m-operations are executed in a single clock period. Functional modules
RET1: (RETirement Stage 1). When a m-operation has been executed and all the preceding conditional branches have been solved, attaches a ready-for-retirement tag to the m-operation
RET2: (RETirement Stage 2). It transfers the results to the architectural machine destination registers when all the preceding machine level instructions have been already committed. Up to 3 m-ops per clock are retired

6. IFU1-IFU2 stages
It transfers a 32 bytes line from the L1 cache to the prefetch queue
IFU1
IFU2
It detects the instruction boundaries within a 16 byte block (half cache line). In the IFU2 any conditional BRANCH address is forwarded to the BTB (physical addresses!). Up to 4 addresses can be in parallel analyzed by the BTB. Initially the BTB is obviously empty and for each decision taken the BTB is updated.
If the branch is predicted as taken the following instructions loaded in the prefetch buffer are removed and the buffer is loaded again with the destination instructions. If the branch is predicted as not taken no change
During the branch execution in the Jump Execution Unit no problem if the branch was correctly predicted, otherwise all following ROB u-ops are cancelled together with their results. The same occurs to all other instructions already in the pipeline. The prefetch buffer is emptied and loaded again with the correct instruction sequence.

7. Branch
The BTB is made of a 4-ways set-associative cache with 512 entries (for each index there are 4 physical branch addresses which are handled)
The prediction algorithm is two-levels: for each BTB entry there is a 4 bit register which stores the behaviours of the last occurrences of the address (BHT).
A further buffer exists in the P6 (the Return Stack Buffer) which stores the return addresses of the speculated subroutines. When a call is speculated (executed before beeing top of the instruction queue) it is not yet sure whether it must be really executed since a previous branch could change the instruction flow. In this case the stack would have been «corrupted». The content of the RSB are transferred to the real stack as soon as the call is actually executed. The RSB consists of 8 entries

8. Compensation queues are needed for different stages speed
Pipeline
Prefetch
Buffer
IFU1
Branch
Target
IFU2
Instruction
lenght
detection
Buffer IN
ORD.
IFU3
(alignment for
the decodimg)
DEC1
Decoder
DEC2
Up to 6
m-ops/clock
||6
RAT
Decoder
queue
Compensation queues are needed for different stages speed
ROB
OUT OF
ORD.
DIS EX
RET1
In the ROB the m-ops are stored in order, are executed OOO, are retired in order IN
ORD.
RET2
Functionally this pipeline is triple

9. IFU3 stage
It prepares the instructions for the three decoders of stage DEC1
Using the «markers» inserted into the 16 bytes block by IFU2, IFU3 rotates, if needed, the three IA instructions so as to aligne them for the next stage
If the three instructions are «simple» no rotation is needed and they are forwarded to the three decoders with no intervention
If in the three instructions there is one «complex» and two «simple» a rotation takes place so as to align the «complex» to decoder 0
If there are two ( o more) «complex» instructions the compiler generated instruction sequence is not optimal and the operations take place in sequence
Instructions types
Simple (converted into a single m-operation): register to register, memory read , etc.
Complex-2 (converted into 2 m-operations): memory write, read/modify, register-memory (sometimes requiring 3 m-operations)
Complex-3: MMX
Complex-4: read/modify/write (ex. add [BP], bx)

10. 20 m-ops queue for the ResStations
Decoding
Fetch and
Aligning
IFU1-IFU2-IFU3
DEC1
Decoder 1
simple
Decoder 2
Decoder 0
complex
16 bytes
Micro
Instruction
Sequencer
MIS
(4+1+1 = 6) x 118 bits
decoded
m-operations
queue
(up to 6 m-ops)
DEC2
RAT
3x118 bits
ROB
3x118 bits
ROB: in the Pentium II
40 slots: loaded with 3 u-ops max per clock
RS 1
RS 2
RS 3
RS 4
RS 5
20 m-ops queue for the ResStations
From the RS to the FU

11. DEC1 and DEC2 Stages DEC1 DEC2 Decoder 0 complex decodes IA
instructions
into
1-4 m-ops
Decoder 1
simple
decodes IA
instructions
into
1 m-op
Decoder 2
simple
decodes IA
instructions
into
1 m-op
The decoder 0 is able to convert in a single clock a complex instruction not longer than 7 bytes generating max 4 m-operations
Decoders 1 e 2 are able to convert in a single clock a «simple» instruction not longer than 7 bytes generating max 1 m-operation
Up to 6 m-operations per clock can be generated
In all other cases MIS The Micro Instruction Sequences is a ROM which stores the m-operations associated to each complex IA instruction which cannot be decoded in a single clock period.
The generated sequences (max 6 m-ops per clock) are directly fed into stage DEC2
If the decoded instruction is a JMP the instruction queue is immediately emptied and reloaded
DEC2
The static BTB (see next slide) is activated if among the m-operations of the preceding clock there is a m-op branch not handled by the dynamic BTB (not detected as branch – it must noticed that here the instructions are already RISC type: two sources and one destination !!!)
The m-ops are queued in the same order as they were produced. The queue has 6 slots

12. Static BTB
The P6 uses a static BTB in the stage DEC2 (the stage which decodes the opcode of the m-ops). It handles the branches not present in the dynamic BTB. It is “static” because uses static rules not depending on the previous instruction history.
yes
no - taken
IP relative ? no
yes
Conditional ?
taken
yes no
Back ?
taken
not taken
The static prediction includes the destination address evaluation too

13. RAT stage Register Allocation Table (Register Renaming) 1 2 . .. 39
EAX
EBX
ECX
EDX
ESI
EDI
ESP
EBP 1 2 . .. 39
RAT
Register Allocation Table
(Register Renaming)

14. ROB stage
The m-ops with the registers renamed in the RAT stage are stored in order three per clock in the ReOrdering Buffer which has 40 slots (much more in the modern processors which however derive from the P6 architecture)
The Reservation Station (the unity which handles the functional units availability) extracts up to 5 m-ops per clock from the ROB (there are 5 ports – busses toward the RS) storing them in a buffer with 20 slots (subdivided per FU) whence they are extracted to be forwarded to the exec units
After the execution the m-ops are stored back into the ROB together with the results. In the ROB there are two pointers : one for the «oldest» m-ops not yet retired and one for the first free slot (if any) where to store the new m-ops
The m-ops are “committed” always three at a time in order. This entails that no m-ops is comitted before a preceding branch has not been solved.
The ROB can be viewed as a “ 40 instructions window”
NB:Very often the «ports» are common to many functional units. The ports are the busses which link – for instance – the ROB with the FU and require always a lot of space in the IC

15. EX Stage (5 functional units only)
PORT2
PORT3
PORT4
Mov EAX, Mem
Typical ìnstructions
Store
Address
Unit
Store
Data
Unit
Load
Unit
5 m-ops
Reorder
Buffer
ROB
Reservation
Station
RS (20 slots)
Mov Mem,EAX
PORT 0
PORT1
INC EAX
Integer
Unit 1
Jump
execution
Unit
FMUL ST0
FDIV ST1
FP Unit
FP Unit
JMP xxxx
Same port
Same port

16. Instructions and m-ops execution
IFU1,IFU2,IFU3
DEC1, DEC2
RAT,ROB
3 CK
2 CK
ID queue
2 CK
Decoders
Prefetch 1
16 bytes 2 1 1
16 bytes 3 2 2 4
Memory address of the first corresponding IA instruction 5
MIS
MIS
Memory
address
renamed
registers (RAT)
m-op op-code
Status 39
ROB (actually the size depends on the processor)

17. m-ops in the ROB
m-ops states in the ROB:
SD: scheduled for execution. The m-op has been inserted in the RS queue but not yet sent to the FU
DP: dispatchable. It is in “pole position” in the EU queue
EX: executed. It is being executed
WB: write back. About to be rewritten in the ROB after the execution. Unblocks other m-ops stalled waiting for its result
RR: ready for retirement. The m-op can be retired
RT: retired. The m-op is being retired
Memory address: it is the memory address of the first byte of the IA32 instruction corresponding to the m-op(s). The address fied for the following m-ops is empty(a IA32 instruction can correspond to many m-ops). An address, therefore, signals a new IA32 instruction
m-op type: branch or not branch
Allocation register: one of the 40 allocation registers
It must be noticed that in case of exception a flag in inserted into the m-op : the excepton is handled only when the m-op is retired. All precedingm-ops are retired (precise interrupt)

18. RESET AL RESET Initial JUMP ID queue Decoders RAT/ROB vvvvvvvviiiiiiii
Prefetch
Streaming
Buffer (32 bytes)
ID queue
Decoders
RAT/ROB
vvvvvvvviiiiiiii
iiiiiiiiiiiiiiii
Jump 8 bytes
v=valid code byte
i=invalid bytes
MIS
renamed
registers (RAT)
Memory
address
Status
m-op op-code 39
N.B. The dynamic BTB is obviously unable to predict the branch

19. Buffer (IFU1) (stores 32 bytes – a cache line)
RESET –IFUi stages
Prefetch Streaming
Buffer (IFU1) (stores 32 bytes – a cache line)
First instruction boundary
Jump
FFFFFFFF:F
FFFFFFF:0
vvvvvvvviiiiiiii
i: not signifcant bytes
iiiiiiiiiiiiiiii
The first instruction is always a backward jump (instruction present in IFU1)
In IFU2 the first instruction boundary is detected (8 bytes). In the remaining 24 bytes other not-signifcant instructions
In IFU3 the first instruction is aligned to 0
NB Each clock a 32 bytes line is read by IFU1. In case of «pipeline traffic jam», because of the decoders, the pipeline stalls

20. RESET Prefetch Streaming ID queue buffer Decoders RAT/ROB JMP MIS
Status
Memory
address
m-op op-code
renamed
registers (RAT) 39

21. RESET –DECi stages The detected instructions are decoded by DEC1.
DEC1 transforms the JMP in a jump m-op (in P6 all jumps are transformed in Branches Taken )
Instructions in the stages from IFU1 to DEC2 are emptied-. This provokes a stall in the pipeline which must reload instructions from the jump address. The m-op is stored in the queue of the decoded instructions

22. RESET RESET Prefetch Streaming buffer ID queue Decoders Branch m-op
RAT/ROB
MIS
Status
Memory
address
m-op op-code
renamed
registers (RAT) 39

23. RESET – RAT stage
The m-op is extracted from the queue of the decoded instructions (which still has the initial order) and inserted in the RAT stage for possible register assignment (not used for branch)

24. RESET RESET Prefetch Streaming ID queue buffer Decoders RAT/ROB MIS
Branch m-op
MIS
Status
Memory
address
m-op op-code
renamed
registers (RAT) 39

25. RESET – ROB and RS stage
The m-op is then sent to the first free ROB slot (normally three of them are trasferred in order to the ROB if there are free slots)
From the ROB the m-op is then sent to the RS queue (4x5 slots) as soon a slot for its FU is available. This operation can be done in parallel to the previous one if there are slots available. This is the case of the first instruction at the RESET

26. RESET RESET Prefetch Streaming buffer ID queue Decoders RAT/ROB MIS
Status
Memory
address
m-op op-code
renamed
registers (RAT)
FFFFFFFF0
branch m-op
none 39

27. RESET – execution and retirement
The RS after a branch execution informs the BTB in order to update the prediction.)
The m-op after the execution is tagged as «executed» in the ROB. If a m-op produces a result (typically a register value) for another m-op (stalled) waiting for it, the waiting m-op status becomes “ready” in the ROB and inserted in the RS as soon as a slot is free
Three m-ops are retired in order bewteen them too per clock.

28. Instructions execution
Stato
Mem. Addr.
m-operation
Renamed register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 EX
non-branch m-op RR
non-branch m-op EX
non-branch m-op
non-branch m-op SD
non-branch m-op
non-branch m-op DP
non-branch u-op RR
branch m-op RT
non-branch m-op
ROB start RT
non-branch m-op RT
non-branch m-op RR
non-branch m-op RR
non-branch m-op RR
non-branch m-op EX A
non-branch u-op WB C
non-branch m-op RR F
non-branch m-op RR
non-branch m-op EX
non-branch m-op DP
non-branch m-op SD
non-branch m-op RR
non-branch u-op RR
non-branch m-op RR B
non-branch m-op RR
non-branch m-op RR
non-branch m-op RR
non-branch m-op WB
non-branch m-op EX
non-branch u-op RR
non-branch m-op RR C
non-branch m-op RR F
non-branch m-op RR
non-branch m-op SD
non-branch m-op RR
non-branch m-op

29. ROB – description (1)
This is the ROB oldest m-op which corresponds to IA instruction whose first byte is at address which will be retired together the m-ops of slots 14 and 15
This m-op (together those in slots 15 and 16) corresponds to an IA instruction 2 bytes long starting at address It must be noticed that the 3 m-ops related to the same IA instruction are NOT retired in the same clock. The address of the first byte of the following IA instruction is (slot 17)
See previous description (m-op now retired)
See previous description (m-op ready for retirement)
This m-op corresponds to a IA instruction one byte long at address It is ready for retirement and will be retired with m-ops in slots 16 and 18
This m-op is the only one generated by the 6 bytes long IA address at addresses It is RR
This m-op corresponds to the two bytes long IA instruction starting at address A. It is now being executed and can last more than a clock. At the end its status will be changed from EX to WB. It will be retired when
Its execution is completedd
The result is written in slot 19
All previous m-ops in the slots have been already retired

30. ROB – description (2) …………………………………………………………….
This m-op is the only one generated by the instruction at addresses C E. Its execution is complete and the result is being written in the slot 20 (status WB). The m-op will be then RR but it will be not retired until the m-ops in the slots 19 and 21 are RR
This m-op (similar to that of slot 22) corresponds to a single byte IA instruction at address F. It is RR but must wait for m-ops in the slots 19 and 20.
Also this m-op (similar to that of slot 21) corresponds to the same single byte IA instruction at address F. It will be retired together with the m-ops in the slots 23 and 24
This m-op derives from IA instruction at addresses It is still being executed (EX). After execution its status will be WB and afterwards it will become RR and retired together with m-ops in the slots 22 and 24 (when they will be RR)
This m-op (as those of the slots 25 and 26) corresponds to the two bytes IA instruction starting at address It is waiting for execution and on the RS queue top (DP status). It will be retired together with m-ops in the slots 22 and 23
This m-op derives form the same instruction of m-op in the slot 24 but its status is SD that is is already in the RS queue but not on top
It derives again from the same IA instruction of the slots 24 and it is RR together with the m-ops in the slots 25 and 27
…………………………………………………………….

31. ROB – description (3) ……………………………………………………………………….
This m-op derives form the one-byte IA instruction at address It is RR and will be retired together with m-ops in the slots 0 and 2 as soon:
The m-ops of the slots 0 and 2 have completed their execution and their results are in the slots 0 and 2
All m-ops in the slots have been already retired
The m-op in the slot 2 derives from IA instruction at hexadecimal addresses (12 bytes).
……………………………………………………………………
This m-op corresponds to the IA instruction at addresses
This m-op is an already executed branch (RR status) corresponding to the IA instruction at address It will be retired together with m-ops of the slots 6 and 8. The branch was predicted as taken and the prediction was detected as correct during the execution, then ..
.. the m-op of this slot derives from the iA instruction at address (branch destination address)
N.B. If the predction had been detected as incorrect the m-op of the slot 8 and all the following m-ops would have been cancelled

32. After retiring13,14,15 ROB start m-operation Renamed register 1 2 3 4
Stato
Mem. Addr.
m-operation
Renamed register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 EX
non-branch m-op RR
non-branch m-op EX
non-branch m-op
non-branch m-op SD
non-branch m-op
non-branch m-op DP
non-branch u-op RR
branch m-op RR
non-branch m-op RR
non-branch m-op
ROB start RR
non-branch m-op EX A
non-branch u-op WB C
non-branch m-op RR F
non-branch m-op RR
non-branch m-op EX
non-branch m-op DP
non-branch m-op SD
non-branch m-op RR
non-branch u-op RR
non-branch m-op RR B
non-branch m-op RR
non-branch m-op RR
non-branch m-op RR
non-branch m-op WB
non-branch m-op EX
non-branch u-op RR
non-branch m-op RR C
non-branch m-op RR F
non-branch m-op RR
non-branch m-op SD
non-branch m-op RR
non-branch m-op