1. OOO execution © Avi Mendelson, 4/2005 1 MAMAS – Computer Architecture 234367 Lecture 7 – Out Of Order (OOO) Avi Mendelson Some of the slides were taken from: (1) Lihu Rapoport (2) Randi Katz and (3) Petterson

2. OOO execution © Avi Mendelson, 4/2005 2 Go beyond IPC=1  Superscalar  VLIW  OOO

3. OOO execution © Avi Mendelson, 4/2005 3 Superscalar - The Pentium© Example  Tries to decode 2 instructions/cycle – Use speculative decoder since this is a CISC machine  Check if we can send two instructions in parallel – Have two instructions decoded – Instruction in “simple Integer”; i.e., can be executed in a single cycle – First instruction is not a jump  The commit is in-order – if one instruction was delayed in the pipe; e.g., cache miss, it stops the other pipe as well  Performance potential – 100% in the ideal case  Actual performance – 20-30% for scientific applications – 5-10% for windows based applications ICACHE Fetch and Decode 2 instructions per cycle V-PipeU-Pipe Commit

4. OOO execution © Avi Mendelson, 4/2005 4 Can we achieve IPC>1 The Very Long Instruction Word (VLIW) approach  Wide issue processor that relies on compiler technology  Multiple functional units, many registers (64-128) – Large multiported register file (about 3 times the number of the functional units)  Simple instruction fetch unit – No checks, direct correspondence between slots & FU  Instruction format – 16 to 24 bits per op – Possible optimizations: share immediate fields (1 per long instruction)

5. OOO execution © Avi Mendelson, 4/2005 5 VLIW - cont  Wide issue processor that relies on compiler to – Packet together independent instructions to be issued in parallel – Schedule code to minimize hazards and stalls  Very long instruction words (3-8 operations) – Can be issued in parallel without hardware checks – If compiler cannot find independent operations, it inserts NOPS  Advantage: Simpler HW for wide issue – Faster clock cycle – Lower design & verification cost  Disadvantages: – Large code size – Requires aggressive compiler – No compatibility between generations

6. OOO execution © Avi Mendelson, 4/2005 6 Can we improve performance ?  In theory “data flow machines” has the best performance – View the program as a parallel operations wait to be executed (will be demonstrate next slide) – Execute instruction as soon as its inputs are ready  So, why computers are Von-Neumann based and not Data-Flow based – Hard to debug – Hard to write Data-Flow programs (need special programming language in order to be efficient)

7. OOO execution © Avi Mendelson, 4/2005 7 Data flow execution – a different approach for high performance computers  Data flow execution is an alternative for Van-Neumann execution. Here, the instructions are executed in the order of their input dependencies and not in the order they appears in the program  Example : assume that we have as many execution units as we need: (1) r1  r4 / r7 (2) r8  r1 + r2 (3) r5  r5 + 1 (4) r6  r6 - r3 (5) r4  r5 + r6 (6) r7  r8 * r4 134 2 5 6 Data Flow Graph We could execute it in 3 cycles

8. OOO execution © Avi Mendelson, 4/2005 8 Data flow execution - cont  Can we build a machine that will execute the “data flow graph”?  In the early 70 th several machines were built to work according to the data-flow graph. They were called “data flow machines”. They were vanished due to the reasons we mentioned before.  Solution: Let the user think he/she are using Van-Neumann machine, and let the system work in “data-flow mode”

9. OOO execution © Avi Mendelson, 4/2005 9 OOOE - General Scheme Fetch & Decode Instruction pool Retire (commit) In-order Execute Out-of-order Most of the modern computers are using OOO execution. Most of them are doing the fetching and the retirement IN- ORDER, but it executes in OUT_OF_ORDER

10. OOO execution © Avi Mendelson, 4/2005 10 Out Of Order Execution Basic idea: – The fetch is done in the program order (in-order) and fast enough in order to “fill-out” a window of instructions. – Out of the instruction window, the system forms a data flow graph and looks for instructions which are ready to be executed:  All the data the instructions are depended on, are ready  Resources are available. – As soon as the instruction is execution it needs to signal to all the instructions which are depend on it that it generate new input. – The instructions are commit in “program’s order” to preserve the “user view”  Advantages: – Help exploit Instruction Level Parallelism (ILP) – Help cover latencies (e.g., cache miss, divide)

11. OOO execution © Avi Mendelson, 4/2005 11 How to convert “In-order” instruction flow into “data flow”  The problems: 1. Data Flow has only RAW dependencies, while OOOE has also WAR and WAW dependencies (as we showed in the last Lecture 5) 2. How to guarantee the in-order completion.  The Solutions: 1. Register Renaming (based on “Tomasulo algorithm”) solves the WAR and WAW dependencies 2. We need to “enumerate” the instructions at decode time (in order) so we know in what order to retire them

12. OOO execution © Avi Mendelson, 4/2005 12 Register Renaming  Hold a pool of physical registers.  Architectural registers are mapped into physical registers – When an instruction writes to an architectural register  A free physical register is allocated from the pool  The physical register points to the architectural register  The instruction writes the value to the physical register – When an instruction reads from an architectural register  reads the data from the latest instruction which writes to the same architectural register, and precedes the current instruction.  If no such instruction exists, read directly from the architectural register. – When an instruction commits  Moves the value from the physical register to the architectural register it points.

13. OOO execution © Avi Mendelson, 4/2005 13 OOOE with Register Renaming: Example Before renaming After renaming (1)r1  mem1t1  mem1 (2)r2  r2 + r1t2  r2 + t1 (3)r1  mem2 t3  mem2 (4)r3  r3 + r1 t4  r3 + t3 (5)r1  mem3t5  mem3 (6)r4  r5 + r1t6  r5 + t5 (7)r5  2t7  2 (8)r6  r5 + 2t8  t7 + 2 After renaming all the false dependencies (WAW and WAR) were removed WAW WAR

14. OOO execution © Avi Mendelson, 4/2005 14 The magic of the modern X86 architectures (Intel, AMD, etc.)  The user view of the X86 machine is as a CISC architecture.  The machine supports this view by keeping the in-order parts as close as possible to the X86 view.  While moving from the In-order part (front-end) to the OOO part (execution), the hardware translates each X86 instruction into a set of uop operations, which are the internal machine operations. These operations are RISC like (load-store based).  During this translation, the hardware performs the register renaming. So, during the execution time it uses internal registers and not the X86 ones. The number of these registers can be changed from one generation to another.  While moving back from the OOO part (execution) to the In-Order part (commit), the hardware translates the registers back to X86, in order to keep for the user a coherent picture.

15. OOO execution © Avi Mendelson, 4/2005 15 OOOE Architecture: based on Pentium-II Write back bus Instruction cache Data cache Bus Interface Unit IFU Instr. Fetch ID Instr. Decode and rename RATROB RS MOB Load/Store Operations Arithmetic Operations Retire (commit) Logic  In Order Front-end 1. Fetch from instruction cache, base on Branch prediction. 2. Decode and rename:  Translate to Uops  Use the RAT table for renaming  Put ALL instructions in ROB  Put all “arithmetic instructions” in the RS queue  Put all Load/Store instructions in MOB  Out-Of-Order 3. Do in Parallel:  Load and store operations are executed based on MOB information  Arithmetic operations are executed based on RS information. 4. All results are written back to ROB, while RS and MOB “steal” values they need  In Order 5. The retire logic (commit logic) moves instructions out of the ROB and updates the architectural registers

16. OOO execution © Avi Mendelson, 4/2005 16 Re-order Buffer (ROB)  Mechanism for keeping the in-order view of the user.  Basic ROB functions – Provide large physical register space for register renaming – Keeps intermediate results, some of them may not be commit if the branch prediction was wrong (we will discuss this mechanism later on) – Keeps information on what is the “Real Register” the commit need to update

17. OOO execution © Avi Mendelson, 4/2005 17 The renaming Algorithm  Each uop allocate a new entry in the ROB. – The entries are allocated in the program’s order – The RAT (register aliasing table) keeps a table that indicates for any architectural register, if the program was executed in-order, what uop (ROB entry) will generate its value.  Every uop that generate value(s) (to register and/or flag) will update the RAT table.  For every input for the uop, we look who is responsible for generate the value. If translation exist in the RAT, we indicate that the value will be retrieved from uop in that ROB entry. If translation does not exist, we retrieve the value from the “architectural register” - RRF (Real Register File)

18. OOO execution © Avi Mendelson, 4/2005 18 Reservation station (RS)  Pool of all “not yet executed” uops – Holds both the uop attributes as well as the values of the input data  For each operand, it keeps indication if it is ready – Operand that need to be retrieved from the RRF is always ready – Operand that waits for another Uop to generate its value, will “lesson” to the WB bus. When the value appears on the bus (the value is always associated with the ROB number it needs to update), all RS entries how need to consume this value, “still” it from the bus and mark the input as ready (this is done in parallel to the ROB update. – Uops whose all operands are ready can be dispatched for execution – Dispatcher chooses which of the ready uops to execute next. If can also do “forwarding”; i.e., schedule the instruction at the same cycle the information is written to the RS entry.  As soon as Uop completes its execution, it is deleted from the RS.  If the RS is full, it stalls the decoder

19. OOO execution © Avi Mendelson, 4/2005 19 Memory Order Buffer (MOB)  Goal – Manipulates the Load and Store operations. If possible, it allows out-of-order among memory operations  Structure similar in concept to ROB  Every memory uop allocates new entry in-order.  Address need to be updated when known  Problem- Memory dependencies cannot be fully resolved statically (memory disambiguation) – store r1,a; load r2,b  can advance load before store – store r1,[r3]; load r2,b  load should wait till r3 is known  In most of the modern processors, Loads may pass loads/stores but Stores must be execute in order (among stores).  For simplicity, this course assumes that all MOB operations are executed in order.

20. OOO execution © Avi Mendelson, 4/2005 20 An example of OOO Execution

21. OOO execution © Avi Mendelson, 4/2005 21 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3

22. OOO execution © Avi Mendelson, 4/2005 22 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3 LD R1,X R2 <- R3 R1 <- R1+R0  I4 I5

23. OOO execution © Avi Mendelson, 4/2005 23 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3 LD R1,X R2 <- R3 R1 <- R1+R0  LD R1,X RB0 M0 LD RB0,X I4 I5 Takes 3 cycles

24. OOO execution © Avi Mendelson, 4/2005 24 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3 LD R1,X R2 <- R3 R1 <- R1+R0  LD R1,X RB0 M0 LD RB0,X R2 <- R3 RB1 RB1 <- R3 RS0 I4 I5

25. OOO execution © Avi Mendelson, 4/2005 25 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3 LD R1,X R2 <- R3 R1 <- R1+R0  LD R1,X RB2 M0 LD RB0,X R2 <- R3 RB1 RB1 <- R3 RS0 R1 <- R1+R0 RB1 <- R3 RS1 I4 RB2 <- RB0+R0 I5

26. OOO execution © Avi Mendelson, 4/2005 26 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3 LD R1,X R2 <- R3 R1 <- R1+R0  LD R1,X RB2 M0 LD RB0,X R2 <- R3 RB1 O.K R1 <- R1+R0 RS1 I4 RB2 <- RB0+R0 I5 Got the value now I4 Cannot execute since the data is not ready yet I4

27. OOO execution © Avi Mendelson, 4/2005 27 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3 LD R1,X R2 <- R3 R1 <- R1+R0  LD R1,X RB2 OK R2 <- R3 RB1 OK R1 <- RB0+R0 RS1 I4 I5 I4 RB2 <- RB0+R0 RS2 I4 I5 RS3 I5

28. OOO execution © Avi Mendelson, 4/2005 28 Instruction Q MOB RS ROB Execute Retire RAT R0 R1 R2 R3 LD R1,X R2 <- R3 R1 <- R1+R0  LD R1,X RB3 R2 <- R3 R1 <- RB1+R0 OK I4 I5 I4 I5 I6 I4 I5 I4I5 I6 rs2 rs3 rs0

29. OOO execution © Avi Mendelson, 4/2005 29 Backup