CS 2204 Spring 2007 Experiment 6 Lab 10 Lab 11 Lab 12 Lab 13.

CS 2204 Spring 2007 Experiment 6 Lab 10 Lab 11 Lab 12 Lab 13

Experiment 6 Lab 10 Outline
Presentation Descriptions of two blocks of the Ppm Digital System Control Unit (the Sequencer) Block 6 (the Machine Player) Individual work Developing Ppm Block 6 Using Term Project Using Experiment 6 Design Checks New handout Experiment 6 Design Checks CS 2204 Spring 2007 Experiment 6 Lab 10-14

Xilinx Project Development Steps
Develop the schematic DESIGN the schematic Design blocks, (sub)blocks Place the components and wires Do integrity TESTs TEST the schematic via functional simulations MODIFY the schematic to correct an error Do a Xilinx IMPLEMENTATION It maps the components to the CLBs of the chip Do timing simulations to TEST the schematic It generates the bit file Download the bit file to the FPGA and test the design on the board It programs the chip What are these components ? Development Cycle on Computers Development Cycle with FPGA chips CS 2204 Spring 2007 Experiment 6 Lab 10-14

CS2204 Components Available components for a new chip Lab design
Generic components Lectures, homework, exams Xilinx components Labs Use Xilinx macros as much as possible Gates Flip-flops Popular digital circuits Gates Flip-flops Popular digital circuits AND OR NOT NAND NOR … D JK T SR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … Try not to use these components AND OR NOT NAND NOR … D JK ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … CS 2204 Spring 2007 Experiment 6 Lab 10-14

Designing a New Chip DESIGN Implement each circuit
One or more Xilinx Design Blocks, XDBs or Xilinx non-programmable macros (not gates and FFs) implement the circuit ? A few gates and FFs here and there ? If yes, draw the schematic and move to the TEST step One or more Programmable Xilinx macros implement the circuit ? A few gates and FFs here and there ? If yes, draw the schematic, program the macros and move to the TEST step CS2204 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Designing a New Chip DESIGN Implement each circuit
Simple enough to be designed quickly using Switching Theory (less than 5 inputs or less than 5 FFs) so a few gates and/or FFs needed ? If yes, draw the schematic and move to the TEST step The circuit can be licensed ? If yes, borrow it, place it and move to the TEST step If no to all the above questions, go back to step 1(b) to partition it further or repartition one level up, two levels up,,, or, all the way up CS2204 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital Systems This first partitioning of a digital system is universal The Ppm is a digital system CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital Systems The Control Unit (Sequencer)
The control unit determines the sequence of microoperations based on the status signals The control unit goes through states In each state, it enables the microoperations of that state to happen in the data unit based on the status signals ► Microoperations must start at the right time with correct inputs and end at the right time with correct outputs  We should not lose data and we should not use old data ► Glitches, gate delays must be accounted for  When we design it, we account for every possible gate delay CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital Systems The Control Unit (Sequencer)
The state register indicates the current state Logic to generate the control signals and the next state more irregular than the Data Unit CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital Systems The Control Unit (Sequencer) design
Hardwiring vs microprogramming Gate networks = random logic = irregular ROM bits generate control signals and NS Highly regular But slower Not as regular as the datapath ROM : Read Only Memory CS 2204 Spring 2007 Experiment 6 Lab 10-14

First partitioning on the Control Unit Control Signal generation Subblock Next State Generation Subblock CS 2204 Spring 2007 Experiment 6 Lab 10-14

Finite state machine (FSM) design technique The sequencer is treated as a state machine A state diagram (with finite number of states) shows which microoperation happens when Each state shows ► Which control signal is active ► Which state to go to next based on status signals Each state has a unique number to identify ► The state register value is the current state number For simple digital systems, one obtains the operation diagram then converts it to a FSM state diagram CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Finite state machine (FSM) technique On paper
Start with the black box view and the textual input/output relationship of the digital system Convert the textual input/output relationship to an operation diagram Convert the operation diagram to a high-level state diagram with microoperations with the same number of states A diagram with finite number of states From the high-level state diagram, obtain the datapath From the high-level state diagram and the datapath, obtain the low-level state diagram Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming ► Hardwiring is acceptable if it is not a complex digital system ► It is the case with the Ppm term project CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Finite state machine (FSM) technique On paper
Implement the sequencer which is treated as a state machine The low-level state diagram (a state diagram with finite number of states) shows which microoperation happens when ► Each state shows  Which control signal is active  Which state to go to next based on status signals ► Each state has a unique number to identify  The state register value is the current state Convert control signal and next state information of the low-level state diagram to sequencer hardware ► Place the counter (state register) +decoder combination if hardwiring is used ► Obtain Expressions  Obtain gate networks of the sequencer ► Place the state register if microprogramming is used ► Obtain a table of microinstructions in 1s and 0s  Program the ROM of the sequencer Start implementing the circuits on computer Start drawing the schematics by using the design on paper CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Textual Input/Output Relationship
Digital System Design Finite state machine (FSM) design example Start with the black box view and the textual input/output relationship of the digital system The black-box view The Textual Input/Output Relationship Starting with the Reset state Input 3 numbers in three successive clock periods Choose the largest of these Add the chosen one and the number on NUM in the fourth clock period Output the result next clock period Repeat these every four clock periods Keep the output value until the next output value is calculated Digital System 8 NUM Clock OUT CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Finite state machine (FSM) design example NUM
Convert the textual input/output relationship to an operation diagram Store 1st number If NUM > 1st number then store NUM 1 2 3 Add largest and NUM then store and output If NUM > current largest then store NUM Digital System 8 NUM Clock OUT After Reset Input 3 numbers on NUM Choose the largest Add the largest and NUM Output the result Repeat every four clock periods Keep the output value till next time CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design NUM OUT CS 2204 Spring 2007
Finite state machine (FSM) design example Convert the operation diagram to a high-level state diagram with microoperations with the same number of states Store 1st number If NUM > 1st number then store NUM 1 2 3 Add largest and NUM then store and output If NUM > current largest then store NUM A  NUM If NUM > A then A  NUM 1 B  A + NUM 3 2 Clock Digital System 8 NUM OUT CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Finite state machine (FSM) design example OUT A
Obtain the datapath from the high-level state diagram OUT A 8 NUM StoreA B 8-bit ADDer Compare Gt StoreB Clock A  NUM If NUM > A then A  NUM 1 B  A + NUM 3 2 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Finite state machine (FSM) design example A NUM
Obtain the low-level state diagram from the high-level state diagram and the datapath StoreA = 1 If Gt == 1 then 1 StoreB = 1 3 2 A  NUM If NUM > A then A  NUM 1 B  A + NUM 3 2 A 8 NUM StoreA B OUT 8-bit ADD Compare Gt StoreB CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Data Unit Control Unit Two control signals
Finite state machine (FSM) design example Decide about how to implement the control unit (sequencer) NUM StoreA = 1 If Gt == 1 then 1 StoreB = 1 3 2 We decide to use hardwiring since it is a relatively simple digital system OUT Data Unit 8 8 Gt StoreA StoreB Control Unit Two control signals One status signal CS 2204 Spring 2007 Experiment 6 Lab 10-14

How do we implement the round robin trace of the states ?
Digital System Design Finite state machine (FSM) design example Convert control signal and next state information of the low-level state diagram to sequencer hardware StoreA = 1 If Gt == 1 then 1 StoreB = 1 3 2 How do we implement the round robin trace of the states ? We need a combination of ► 2-bit Up counter ► 2-to-4 Decoder To keep track of the current state CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Finite state machine (FSM) design example
Convert control signal and next state information of the low-level state diagram to sequencer hardware  Place the counter+decoder combination if hardwiring is used We need a combination of ► 2-bit Up counter ► 2-to-4 Decoder To keep track of the current state 2-bit up counter Q0 Q1 clock 2-to-4 Decoder A0 A1 D0 D1 D2 D3 S0 S1 S2 S3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

► It is state 0 OR ► It is state 3 StoreB = S3 CS 2204 Spring 2007
Digital System Design Finite state machine (FSM) design example Convert control signal and next state information of the low-level state diagram to sequencer hardware Place the counter+decoder combination if hardwiring is used Obtain Expressions StoreA = 1 If Gt == 1 then 1 StoreB = 1 3 2 StoreA is 1 when ► It is state 0 OR ► It is state 1 AND Gt = 1 OR ► It is state 2 AND Gt = 1 StoreA = S0 + S1Gt + S2Gt StoreB is when ► It is state 3 StoreB = S3 2-bit up counter Q0 Q1 clock 2-to-4 Decoder A0 A1 D0 D1 D2 D3 S0 S1 S2 S3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Digital System Design Finite state machine (FSM) design example
Convert control signal and next state information of the low-level state diagram to sequencer hardware  Place the counter+decoder combination if hardwiring is used Obtain Expressions Obtain gate networks of the sequencer StoreA = S0 + S1Gt + S2Gt StoreA S1 Gt S0 S2 StoreB S3 StoreB = S3 2-bit up counter Q0 Q1 clock 2-to-4 Decoder A0 A1 D0 D1 D2 D3 S0 S1 S2 S3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Control Unit Datapath A NUM B OUT CS 2204 Spring 2007
Digital System Design Finite state machine (FSM) design example Final digital system design on paper Start implementing the circuits on computer Start drawing the schematics by using the design on paper A 8 NUM StoreA B OUT 8-bit ADDer Compare Gt StoreB Clock Datapath StoreA S1 Gt S0 S2 StoreB S3 2-bit up counter Q0 Q1 clock 2-to-4 Decoder A0 A1 D0 D1 D2 D3 Control Unit CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Term Project The black-box view
A large number of FFs are used ! The Ppm is partitioned based on major operations First partitioning of the digital system Control Unit Data Unit Second partitioning (Data Unit partitioning) Interfacing to the input/output devices Handling human player’s play Controlling display operations based on game rules Calculating new player points Determining the machine player play CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Digital System Partitioning
CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Control Unit Block 1, the Control Unit (the sequencer)
It controls the Data Unit It determines the sequence of microoperations Which microoperation happens when Block 1 17 How can we implement the block ? CS 2204 Spring 2007 Experiment 6 Lab 10-14

The control unit determines the sequence of microoperations based on the status signals Implemented by using the FSM technique Uses hardwiring Gate networks generate control signals Partitioned into Control Signal generation Subblock and Next State Generation Subblock CS 2204 Spring 2007 Experiment 6 Lab 10-14

Signal Generation Subblock Control signals Next State Generation Subblock Counter- Decoder combination to keep track of the current state CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Control Unit Block 1, the Control Unit (the sequencer) Control
Important outputs of the block Clear : Clear all FFs, registers and counters in state 0 (reset) Stdisp : Store on a position display in state 2 or 5 Selplyr : Select player It is 0 when it is state 0, 1, 2 and 3 It is 1 when it is state 4, 5 and 6 Clearp2ffs : Clear all Player 2 FFs, registers and counters After reset After it plays Rdrwdsel : Random reward selected It is 1 in state 1 or in state 4 Add : Add RD to a display It is 1 in state 1 or 4 Control signals CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Control Unit Block 1, the Control Unit (the sequencer) Control
Important outputs of the block Stp1pt : Store new points on the Player 1 points register in state 2 Cleartoplay : Clear FFs and registers in Block 1 and Block 5 It is 1 after reset and after a player plays Stp2pt : Store new points on the Player 2 points register in state 5 Grd : Get a new random digit Bpds : Blink slowly either the display played after a direct play or all four displays after a player has won the game in state 3 and state 6 Bpdf : Blink fast a display if the display has an overflow after an addition in state 3 and state 6 S4 : When it is 1, it indicates the current state is state 4 The course web site machine player checks it to see if it is its turn STR : The current state number Control signals CS 2204 Spring 2007 Experiment 6 Lab 10-14

Experiment 6 Experiment 6 targets Block 6
There is a black box, macro, to implement : M3 M1 M2 M3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Data Unit Block 6, Machine Play Block : Macro 3, M3
Main goal : play as the machine player Generate eight outputs to play correctly Eight specific outputs must be generated no matter what the machine playing strategy is Block 6 ? 8 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Outputs of the block P2SEL : 4 bits indicating on which position the machine player has played Only one of the lines can be 1 to play on a position P2add : A line indicating if the machine player adds to a position P2rdrwd : A line indicating if the machine selects the random reward P2played : A line indicating that the machine player has played the random digit on a position When it is 1, only one of P2SEL lines can be 1 P2skip : A line indicating that the machine player has skipped the play When it is 1, P2played must be 0 and vice versa These eight outputs must be generated no matter what the machine playing strategy is CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development
Plays as the machine player On paper Start with the black box view where the outputs are fixed and the input/output relationship Understand the game rules and how the machine player has to interact with the rest of the Ppm digital system Determine the playing strategy (intelligence) Convert the textual input/output relationship (including the playing strategy) to an operation diagram Convert the playing strategy to major operations Partition Block 6 into subblocks Operation diagram implies the machine player goes through steps taking several clock periods The operation diagram also implies that the Block 6 is a tiny digital system itself Otherwise, an operation table is obtained Convert the operation diagram to a high-level state diagram with microoperations with the same number of states A diagram with finite number of states Distribute microoperations to states How can we implement the block ? CS 2204 Spring 2007 Experiment 6 Lab 10-14

On paper From the high-level state diagram, obtain the datapath Continue to partition the datapath into subblocks Design each (sub)block Implement microperations in datapath hardware From the high-level state diagram and the datapath, obtain the low-level state diagram Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming Hardwiring is acceptable if it is not a complex digital system : It is the case with the Ppm term project Implement the sequencer which is treated as a state machine Design the sequencer Start moving the circuits of Block 6 to the computer Copy the exp5 folder and paste it as exp6 Start drawing the schematics by using the design on paper Label the components CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start with the black box view where the outputs are fixed and the input/output relationship Understand the game rules and how the machine player has to interact with the rest of the Ppm digital system Determine the playing strategy (intelligence) Machine Player P2SEL 4 P2played P2skip P2add . P2rdrwd CS 2204 Spring 2007 Experiment 6 Lab 10-14

Machine Player Block 6, Machine Play Block Development .
Start with the black box view where the outputs are fixed and the input/output relationship Machine Player P2SEL 4 P2played P2skip P2add . P2rdrwd Must generate the eight outputs for correct operation The Ppm will stay in state 4 when the machine thinks : both P2played and P2skip are zero It stays in state 4 at least one Sysclk period The selection of inputs depends on the strategy and the implementation CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start with the black box view where the outputs are fixed and the input/output relationship If the random digit is played P2SEL, P2add and P2rdrwd are determined & P2played = 1 No more than one of P2SEL can be one at a time If the random digit is not played The machine player skips : P2skip = 1 P2played and P2skip are not 1 at the same time If both P2played and P2skip are 0, it means the machine player is thinking Developing Block 6 is determining these eight outputs Additional outputs can be generated depending on the strategy These extra outputs are used by the other five blocks The five blocks need to be changed ! Not recommended ! CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start with the black box view where the outputs are fixed and the input/output relationship Understand the game rules and how the machine player has to interact with the rest of the Ppm digital system Determine the playing strategy (intelligence) Play aggressively : Machine Player P2SEL 4 P2played P2skip P2add . P2rdrwd We know the game rules already ! Playing Strategy Play on the (rightmost) largest reward position with an addition (if equal) and request a random reward (if adjacency) CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start with the black box view where the outputs are fixed and the input/output relationship Determine the playing strategy (intelligence) Play aggressively : Always plays (does not skip at all) Plays on the largest reward points position with an addition (no direct playing at all) If two or more positions have the same reward, selects the rightmost one (can also select randomly, or round robin, etc.) If there is an adjacency, it requests a random reward (does not play again) Playing Strategy Play on the (rightmost) largest reward position with an addition (if equal) and request a random reward (if adjacency) CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start with the black box view where the outputs are fixed and the input/output relationship Determine the playing strategy (intelligence) The second machine player of the machine vs. machine project Selectively aggressive Other candidate strategies The flowchart of the playing strategy If there is an adjacency, it requests the random reward CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start with the black box view where the outputs are fixed and the input/output relationship Determine the playing strategy (intelligence) Non-intelligent machine player strategies Play in a permanently fixed way : always play on the rightmost position which does not have a display overflow. If all positions result in display overflows, skips Play randomly : when it is time to play, stop a freely running 2-bit counter and play on that position Play in a fixed way - round robin fashion : every time it is the turn, increment a 2-bit counter and play on that position Play on the first 1-adjacency position from right to left Other candidate strategies CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram Convert the playing strategy to major operations Partition Block 6 into subblocks Operation diagram implies the machine player goes through steps taking several clock periods The operation diagram also implies that the Block 6 is a tiny digital system itself Otherwise, an operation table is obtained The goal is to develop an intelligent machine player It gathers information about the current situation Decides how to play Therefore, Block 6 must have at least two subblocks Information Gathering Subblock Decision Making Subblock However, these two major operations are done in several step and so another major operation, controlling major operation and a new subblock, a Sequencing Subblock is needed CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram Play aggressively : There are at least two major operations: gather reward information and decide which position to play We have then an information gathering subblock and a decision making subblock ? The information gathering subblock obtains the reward points with addition on the four positions ? The decision making subblock compares the eight reward points to see which one is the largest ? Why do we need the controlling major operation and so the sequencing subblock ? CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram How can we gather the four reward points and decide ? The information gathering subblock has to obtain the adjacency with addition and then the reward points These are simplified versions of the Adjacency and Reward Calculation Subblocks of Block 5 ►Tightly coupling Block 5 and Block 6 can be beneficial In parallel ? Then four Adjacency circuits and four Reward Calculation circuits are needed ! ► Can the limit of the FPGA chip be exceeded ? In sequence ? Then a sequencing circuit is needed to get the reward points for each position one by one ! ► A new subblock is needed as the mini sequencer  Can the FPGA chip limit be exceeded ? CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram How can we compare the four reward points and decide ? In parallel ? Even if the reward points are obtained sequentially ? ► Yes ! We have to have three 8-bit comparators and associated control circuits ! ► Can the limit of the FPGA chip be exceeded ? In sequence ? Even if the reward points are obtained in parallel ? We need to have a sequencing circuit to compare the reward points for each position one by one ! ► A new subblock is needed as the mini sequencer  Can the FPGA chip limit be exceeded ? CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram Here are the four choices to implement the strategy : Parallel gather and parallel compare+decide The chip limit can be exceeded No need for a sequencer ! An operation table instead of an operation diagram is obtained Parallel gather and sequential compare+decide Store all four reward points on four registers and then compare them one by one ! ► A sequencing circuit is needed as the mini sequencer ► It does not make sense to choose this CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram Here are the four choices to implement the strategy : Sequential gather and parallel compare+decide A sequencing circuit is needed to get reward points on four registers one by one ► The registers are compared in parallel ► It does not make sense to choose this Sequential gather and sequential compare+decide A sequencing circuit is needed to get reward points, compare with the previous largest reward and update the reward ► The simplest of the four is this one ! CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram Parallel gather and parallel compare+decide No sequencer : All combinational An operation table is obtained We will skip getting the operation table to save time ! The operation table has the major operations There is only the datapath ! The datapath is partitioned based on the major operations on the operation table The machine player decides in one clock period CS 2204 Spring 2007 Experiment 6 Lab 10-14

Machine Player CS 2204 Spring 2007 Experiment 6 Lab 10-14
Block 6, Machine Play Block Development Convert the textual input/output relationship (including the playing strategy) to an operation diagram Parallel gather and parallel compare+decide : no sequencer ! All combinational The machine player decides in one clock period 4 Determine reward points for four positions and decide where to play 4 Player 2 plays on a position Player 2 skips NPDISP 16 P2SEL DISP 16 Machine Player P2add S4 P2rdrwd Clearp2ffs P2played Sysclk P2SEL = number of the position with the largest reward  P2add = 1, P2rdrwd = 1, P2played = 1, P2skip = 0 4 Player 2 plays on a position Player 2 skips P2skip Player 2 spends One Sysclk periods to think CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the operation diagram to a high-level state diagram with microoperations with the same number of states Parallel gather and parallel compare+decide : no sequencer ! All combinational There is only the datapath ! This step is not needed and so skipped ! CS 2204 Spring 2007 Experiment 6 Lab 10-14

From the high-level state diagram, obtain the datapath Continue to partition the datapath into subblocks Design each (sub)block Implement microperations in datapath hardware Parallel gather and parallel compare+decide : no sequencer! All combinational There is only the datapath ! Partition the datapath to subblocks The datapath subblocks are designed CS 2204 Spring 2007 Experiment 6 Lab 10-14

From the high-level state diagram, obtain the datapath Parallel gather and parallel compare+decide : no sequencer ! All combinational Continue to partition the datapath into subblocks The datapath subblocks are designed Gather Four Reward Points NPDISP 16 8 P0RWD P1RWD P2RWD P3RWD Compare and Select One S4 DISP Sysclk Clearp2ffs P2add P2SEL 4 P2played P2skip P2rdrwd CS 2204 Spring 2007 Experiment 6 Lab 10-14

P0RWD P0RWD P0RWD P0RWD CS 2204 Spring 2007 Experiment 6 Lab 10-14
Block 6, Machine Play Block Development From the high-level state diagram, obtain the datapath Parallel gather and parallel compare+decide : no sequencer ! All combinational Continue to partition the datapath into subblocks The datapath subblocks are designed 4 NPDISP Position 0 Reward Determination 8 8 4 12 DISP P0RWD P0RWD Compare & Select One PXRWD P2SEL 4 NPDISP Position 1 Reward Determination 2 8 Compare and Select One 12 P2add DISP P0RWD P1RWD PXNUM 4 P2rdrwd NPDISP Position 2 Reward Determination 8 8 12 DISP P0RWD P2RWD Compare & Select One P2played PYRWD 4 2 NPDISP Position 3 Reward Determination 8 P2skip 12 P0RWD PYNUM DISP P3RWD S4 Sysclk Clearp2ffs CS 2204 Spring 2007 Experiment 6 Lab 10-14

CS 2204 Spring 2007 Experiment 6 Lab 10-14
Block 6, Machine Play Block Development From the high-level state diagram, obtain the datapath Parallel gather and parallel compare+decide : no sequencer ! All combinational Continue to partition the datapath into subblocks The datapath subblocks are designed Position 0 Adjacency NPDISP[3-0] 4 DISP[15-4] 12 8 P0RWD 2 P0NSD Reward Calculation Position 1 NPDISP[7-4] DISP[15-8 ; 3-0] P1RWD P1NSD Position 2 NPDISP[11-8] DISP[15-12 ; 7-0] P2RWD P2NSD Position 3 NPDISP[15-12] DISP[11-0] P3RWD P3NSD CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development From the high-level state diagram, obtain the datapath Parallel gather and parallel compare+decide : no sequencer ! All combinational Continue to partition the datapath into subblocks The datapath subblocks are designed 8 P0RWD P1RWD Compare PXRWD 2 PXNUM Select 1 P2RWD P3RWD PYRWD PYNUM 3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development From the high-level state diagram, obtain the datapath Parallel gather and parallel compare+decide : no sequencer ! All combinational Continue to partition the datapath into subblocks The datapath subblocks are designed S4 R0 R1 2-to-4 Decoder A0 A1 E D0 D1 D2 D3 Compare Result & Select P2SEL0 P2SEL1 P2SEL2 P2SEL3 8 PXRWD 2 PXNUM PYRWD PYNUM 4-bit register CE C Q0 Q1 Q2 Q3 Sysclk I0 I1 I2 I3 CLR Clearp2ffs P2played P2skip P2add 1 P2rdrwd Always plays on a position : it does not skip Plays on the position with the largest reward by doing an addition : it does not play directly If two or more positions have the same reward, plays on the rightmost position If there is an adjacency, request the random reward CS 2204 Spring 2007 Experiment 6 Lab 10-14

From the high-level state diagram and the datapath, obtain the low-level state diagram This step is skipped ! Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming Hardwiring is acceptable if it is not a complex digital system : It is the case with the Ppm term project Implement the sequencer which is treated as a state machine Design the sequencer Start moving the circuits of Block 6 to the computer Copy the exp5 folder and paste it as exp6 Start drawing the schematics by using the design on paper Label the components Always plays on a position : it does not skip Plays on the position with the largest reward by doing an addition : it does not play directly If two or more positions have the same reward, plays on the rightmost position If there is an adjacency, request the random reward CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start implementing the circuits of Block 6 on computer Parallel gather and parallel compare+decide : no sequencer ! All combinational Copy the exp5 folder and paste it as exp6 Start drawing the schematics by using the design on paper Perform simulations Sysclk S4 S5 R1,R0 P2SEL 0010 Player 2 plays : One Sysclk period P2played S6 Clearp2ffs CS 2204 Spring 2007 Experiment 6 Lab 10-14

Convert the textual input/output relationship (including the playing strategy) to an operation diagram Sequential gather and Sequential compare+decide An operation diagram is needed Convert the playing strategy to major operations Partition Block 6 into subblocks Block 6 is a tiny digital system itself The machine player takes several clock periods to make a decision CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development Convert the textual input/output relationship (including the playing strategy) to an operation diagram Sequential gather and Sequential compare+decide An operation diagram is needed Determine position 0 reward & record the position number Determine position 1 reward, compare with position 0, keep it if it is larger & record the position number Determine position 2 reward , compare with the previous, keep it if it is larger & record the position number Determine Position 3 Reward , compare with the previous, keep it if it is larger, record the position number P2st0 4 Player 2 plays on a position Based on the stored information select the position to play Player 2 skips P2st1 P2st2 P2str3 P2st4 Machine Player RWD 8 S4 Clearp2ffs Sysclk P2add P2SEL 4 P2played P2skip P2rdrwd Player 2 spends FIVE Sysclk periods to think CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development Convert the operation diagram to a high-level state diagram with microoperations with the same number of states Sequential gather and Sequential compare+decide A diagram with finite number of states Distribute microoperations to states P2SEL =0001 ; P2played = 0 ; P2skip = 0 ; P2add = 1 ; LRGRWD  RWD ; POS  0001 4 Player 2 plays on a position P2SEL =0010 ; P2played = 0 ; P2skip = 0 ; P2add = 1 ; If RWD > LRGRWD then LRGRWD  RWD ; POS  0010 P2SEL =0100 ; P2played = 0 ; P2skip = 0 ; then LRGRWD  RWD ; POS  0100 P2SEL =1000 ; P2played = 0 ; P2skip = 0 ; then LRGRWD  RWD ; POS  1000 P2SEL = POS ; P2add = 1 ; P2rdrwd = 1 ; P2played = 1 ; P2skip = 0 Player 2 skips P2st0 P2st1 P2st2 P2str3 P2st4 4 NPDISP 16 P2SEL DISP 16 Machine Player P2add S4 P2rdrwd Clearp2ffs P2played Sysclk P2skip Player 2 spends FIVE Sysclk periods to think CS 2204 Spring 2007 Experiment 6 Lab 10-14

CS 2204 Spring 2007 Experiment 6 Lab 10-14 Gather reward points
Block 6, Machine Play Block Development From the high-level state diagram, obtain the datapath Sequential gather and Sequential compare+decide Continue to partition the datapath into subblocks Design each (sub)block Implement microperations in datapath hardware Eight control signals One status signal 4 P2SEL 8 RWD Gather reward points Compare them Select one P2add P2rdrwd Sysclk P2played P2skip Gt Play Store Clr P2s3 P2s2 P2s1 P2s0 Sysclk Clearp2ffs Sequencing S4 Always plays on a position : it does not skip Plays on the position with the largest reward by doing an addition : it does not play directly If two or more positions have the same reward, plays on the rightmost position If there is an adjacency, request the random reward CS 2204 Spring 2007 Experiment 6 Lab 10-14

Datapath CS 2204 Spring 2007 Experiment 6 Lab 10-14
Block 6, Machine Play Block Development From the high-level state diagram, obtain the datapath Sequential gather and Sequential compare+decide Continue to partition the datapath into subblocks Design each (sub)block Implement microperations in datapath hardware P2s0 D0 Q0 POS0 P2s0 P2SEL0 Datapath P2s1 D1 Q1 POS1 4-bit Register P2s1 P2s2 D2 Q2 POS2 P2SEL1 P2s3 D3 Q3 POS3 P2s2 P2SEL2 Store CE Sysclk Play P2s3 C P2SEL3 RWD 8 D LRGRWD CLR S4 8-bit Register Q CE P2played Clr Store 8 Play P2skip C 1 RWD Sysclk 8 A P2add 8-bit Comparator A>B CLR P2rdrwd 8 Gt Clr LRGRWD B CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development From the high-level state diagram and the datapath, obtain the low-level state diagram Sequential gather and Sequential compare+decide P2s0 = 1 Store = 1 P2s1 = 1 If RWD > LRGRWD then Store = 1 P2st0 4 Player 2 plays on a position Play = 1 Player 2 skips P2st1 P2st2 P2str3 P2st4 P2s2 = 1 P2s3 = 1 P2SEL =0001 ; P2played = 0 ; P2skip = 0 ; P2add = 1 ; LRGRWD  RWD ; POS  0001 4 Player 2 plays on a position P2SEL =0010 ; P2played = 0 ; P2skip = 0 ; P2add = 1 ; If RWD > LRGRWD then LRGRWD  RWD ; POS  0010 P2SEL =0100 ; P2played = 0 ; P2skip = 0 ; LRGRWD  RWD ; POS  0100 P2SEL =1000 ; P2played = 0 ; P2skip = 0 ; LRGRWD  RWD ; POS  1000 P2SEL = POS ; P2add = 1 ; P2rdrwd = 1 ; P2played = 1 ; P2skip = 0 Player 2 skips P2st0 P2st1 P2st2 P2str3 P2st4 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Decide about how to implement the control unit (sequencer) Sequential gather and Sequential compare+decide Hardwiring or microprogramming ? Hardwiring is acceptable if it is not a complex digital system : It is the case with the Ppm term project P2s0 = 1 Store = 1 P2s1 = 1 If RWD > LRGRWD then Store = 1 P2st0 4 Player 2 plays on a position Play = 1 Player 2 skips P2st1 P2st2 P2str3 P2st4 P2s2 = 1 P2s3 = 1 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Implement the sequencer which is treated as a state machine Sequential gather and Sequential compare+decide Design the sequencer P2s0 = 1 Store = 1 P2s1 = 1 If RWD > LRGRWD then Store = 1 P2st0 4 Player 2 plays on a position Play = 1 Player 2 skips P2st1 P2st2 P2str3 P2st4 P2s2 = 1 P2s3 = 1 A counter + decoder combination is needed to keep track of the states CS 2204 Spring 2007 Experiment 6 Lab 10-14

Implement the sequencer which is treated as a state machine Sequential gather and Sequential compare+decide Design the sequencer 3-bit up counter CE C CLR Q0 Q1 Q2 P2skip P2played S4 Sysclk Clearp2ffs P2streg0 P2streg1 P2streg2 A0 A1 E1 P2streg Gt Clr Store 2-to-4 Decoder D0 D1 D2 D3 P2s0 P2s1 P2s2 P2s3 E0 Play Use this counter+decoder circuit if your machine player has five states CS 2204 Spring 2007 Experiment 6 Lab 10-14

Datapath Control Unit CS 2204 Spring 2007 Experiment 6 Lab 10-14
Block 6, Machine Play Block Development Start implementing the circuits of Block 6 on computer Sequential gather and Sequential compare+decide Final digital system design on paper Datapath Control Unit CS 2204 Spring 2007 Experiment 6 Lab 10-14

Start implementing the circuits of Block 6 on computer Sequential gather and Sequential compare+decide Copy the exp5 folder and paste it as exp6 Start drawing the schematics by using the design on paper Perform simulations Do not forget to store P2SEL, P2add and P2rdrwd signals is state 4 so that they can be used in states 5 and 6 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development Start implementing the circuits of Block 6 on computer Sequential gather and Sequential compare+decide Perform simulations LRGRWD Position 1 Reward Sysclk S4 S5 P2s0 P2s1 P2s2 P2s3 Play RWD Greater Store P2SEL 0001 0010 0100 1000 Player 2 thinks and plays RD : 5 Sysclk periods P2played CS 2204 Spring 2007 Experiment 6 Lab 10-14

The implementation at the course web site Gathers substantial amount of information to decide 49 inputs and 8 outputs Block 6 49 8 How is it designed ? CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Data Unit Block 6, Machine Play Block : Macro 3, M3 Block 6
The implementation at the course web site Block 6 49 8 CS 2204 Spring 2007 Experiment 6 Lab 10-14

The Ppm Data Unit Block 6, Machine Play Block : Macro 3, M3 M3
The implementation at the course web site M3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

The implementation at the course web site Three major operations Information gathering about the current situation ► Information Gathering Subblock Decision making about what to do with the random digit ► Decision Making Subblock Controlling the operations in the block ► Sequencing Subblock CS 2204 Spring 2007 Experiment 6 Lab 10-14

Course web site machine player Start with the black box view where the outputs are fixed and the input/output relationship Understand the game rules and how the machine player has to interact with the rest of the Ppm digital system Determine the playing strategy (intelligence) CS 2204 Spring 2007 Experiment 6 Lab 10-14

Course web site machine player Start with the black box view where the outputs are fixed and the input/output relationship is as follows Determine the playing strategy (intelligence) Play for now and future : Play differently for different game situations to eventually win the game ►If the machine player has (224)10 or more points or if it does not have (64)10 or more points than the human player, it plays aggressively If the largest reward points position is not equal to the largest adjacency position it plays on the largest reward points  If the largest reward points position is equal to the largest adjacency position it plays on the largest adjacency position  If displays are 8 or higher, does not request a random reward  If displays are less than 8, requests a random reward ► Otherwise, if there is an adjacency, it plays for the largest adjacency without a random reward ► Otherwise, if there is a display that is zero, it plays on it if RD is not zero ► Otherwise, it plays aggressively for the largest reward points CS 2204 Spring 2007 Experiment 6 Lab 10-14

Block 6, Machine Play Block Development Course web site machine player Machine playing strategy CS 2204 Spring 2007 Experiment 6 Lab 10-14

Course web site machine player Convert the textual input/output relationship (including the playing strategy) to an operation diagram Convert the playing strategy to major operations Partition Block 6 into subblocks The machine player gathers substantial amount of information about the game and then decides how to play It has an information gathering subblock and an decision making subblock It gathers the information sequentially and so it has a sequencing subblock ►Sequential gather+compare and parallel decide An operation diagram is needed Operation diagram implies the machine player goes through steps taking several clock periods The operation diagram also implies that the Block 6 is a tiny digital system itself CS 2204 Spring 2007 Experiment 6 Lab 10-14

Course web site machine player Convert the textual input/output relationship (including the playing strategy) to an operation diagram Convert the playing strategy to major operations If the largest reward points position is not equal to the largest adjacency position it plays on the largest reward points, otherwise it plays on the largest adjacency position and if displays are 8 or higher, does not request a random reward, otherwise, requests a random reward If the machine player has (224)10 or more points or if it does not have (64)10 or more points than the human player, it plays aggressively Otherwise, If there is an adjacency, it plays for the largest adjacency without a random reward, otherwise, if there is a display that is zero, it plays on it if RD is not zero, otherwise, it plays aggressively for the largest reward points CS 2204 Spring 2007 Experiment 6 Lab 10-14

Course web site machine player Convert the textual input/output relationship (including the playing strategy) to an operation diagram Convert the playing strategy to major operations Sequential gather+compare, parallel decision making CS 2204 Spring 2007 Experiment 6 Lab 10-14

Course web site machine player Implement the sequencer which is treated as a state machine Design the sequencer A counter + decoder combination is needed to keep track of the states The major portion of the Sequencing Subblock Use this counter+decoder circuit if your machine player has nine states CS 2204 Spring 2007 Experiment 6 Lab 10-14

Developing Machine Player
Course web site machine player Start implementing the circuits on computer Final digital system design on computer CS 2204 Spring 2007 Experiment 6 Lab 10-14

Implementing the machine player, Block 6, M3 The timetable for the rest of the semester Students will submit the Experiment 6 project which will include the implementation of Block 5 Block 6 The deadline : Friday, April 27, 2007 CS 2204 Spring 2007 Experiment 6 Lab 10-14

CS2204 Lab Students will receive a lab grade
5 % of the term grade based on Their lab attendance Arrival and departure Cooperation with partners Concentration on the lab work CS 2204 Spring 2007 Experiment 6 Lab 10-14

After you determine components to use
► Draw the components ► Draw the output wires of the components ► Draw the input wires of the components Do not leave the lab before your partners finish ► Help your partners complete today’s project Read slides on the Ppm, Project Manager, Schematic design and other related topics CS 2204 Spring 2007 Experiment 6 Lab 10-14

Today’s Individual Xilinx Work
We will develop (implement) M3, Block 6 of the term project We will replace the machine player, Macro M3 with our own circuits Read slides on the Ppm, Project Manager, Schematic design and other related topics Help your partners complete today’s project CS 2204 Spring 2007 Experiment 6 Lab 10-14

Today’s Individual Xilinx Lab Work
Copy the exp5 folder and paste it in the cs2204 folder as the exp6 folder Open the Ppm project in exp6 Look at the six Ppm schematics If you copy a project completely as we did and then open its schematics, the schematics will be all Non-Project Therefore, close all these schematics and close the schematics window Then, open the schematics one by one on the Project Manager window, by double clicking on the schematic name on the upper left side Place your team info on the schematics on schematic 1 : ppm1.sch CS 2204 Spring 2007 Experiment 6 Lab 10-14

Save schematic 1 Switch to schematic 6 Zoom into the center area containing the machine player There is a user defined macro with component label M3 See ppm6.sch on the next slide CS 2204 Spring 2007 Experiment 6 Lab 10-14

Ppm Schematic 6 M3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Analyze Macro M3 by reading the slides of this presentation and the term project handout Perform functional simulations on Macro M3 Record your test vectors to use later Search for the inputs and outputs of the Counter by clicking on the Query window button on top of the schematic sheet to confirm your findings in part (9) Delete Macro M3 in schematic Do not delete the wires Save schematic 6, ppm6.sch See modified ppm6.sch on the next slide CS 2204 Spring 2007 Experiment 6 Lab 10-14

Ppm Schematic 6 Macro M3 deleted CS 2204 Spring 2007 Experiment 6 Lab 10-14

Create space in the area by moving the wires in schematic 6 Draw the circuit of Macro M3 in the same area in schematic 6 First, do the design on paper Start with the black box view where the outputs are fixed and the input/output relationship Understand the game rules and how the machine player has to interact with the rest of the Ppm digital system Determine the playing strategy (intelligence) ► Draw a flowchart Convert the textual input/output relationship (including the playing strategy) to an operation diagram Decide about the parallel/sequential implementation issue Get the subblocks Convert the playing strategy to major operations CS 2204 Spring 2007 Experiment 6 Lab 10-14

Today’s Xilinx Lab Work
Draw the circuit of Macro M3 in the same area in schematic 6 Convert the operation diagram to a high-level state diagram with microoperations with the same number of states If sequential gather and Sequential compare+decide is decided ► A diagram with finite number of states ► Distribute microoperations to states From the high-level state diagram, obtain the datapath Sequential gather and Sequential compare+decide Design each (sub)block Implement microperations in datapath hardware From the high-level state diagram and the datapath, obtain the low-level state diagram If Sequential gather and Sequential compare+decide is chosen Decide about how to implement the control unit (sequencer) Hardwiring or microprogramming ? Choose hardwiring CS 2204 Spring 2007 Experiment 6 Lab 10-14

Draw the circuit of Macro M3 in the same area in schematic 6 Implement the sequencer which is treated as a state machine Design the sequencer ► Use the 5-state or 9-state counter+decoder combinations given on previous slides Move the design to the computer ≡ Implement Block 6 on computer Plan where to place the subblocks on the screen Start drawing the schematics First place the components, then their outputs and then their inputs CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform an integrity test to check for errors Perform functional simulations on your circuit to verify that it is working Use the test vectors you recorded in step 10 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Do a Xilinx IMPLEMENTATION Make sure there are no errors Make sure the IMPLEMENTATION options are changed so that a better IMPLEMENTATION is done Read the Implementation Log File Confirm that the warnings are acceptable The number of warnings does not have to be 12 The FPGA chip utilization does not have to be 89% The utilization depends on the strategy, the intelligence of the machine player designed CS 2204 Spring 2007 Experiment 6 Lab 10-14

Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly If it does not work, inspect your circuit in Block 6 and correct your circuit CS 2204 Spring 2007 Experiment 6 Lab 10-14

Completing Block 6 After drawing the schematics, simulating circuits separately and testing them on the FPGA board Label the components The subsubblocks and the subblocks are separated by lines and labelled The circuit is beautified The schematic is saved again Functional simulations of the subblocks are done again A Xilinx IMPLEMENTATION is done again Downloading to the FPGA board and testing are done again CS 2204 Spring 2007 Experiment 6 Lab 10-14

Completing Block 6 After drawing the schematics, simulating circuits separately and testing them on the FPGA board Fill out a Project 6 Check List Handout and then signal to a TA to submit your project Your project will be copied to a zip disk by the TA Once copied, open the project on the zip disk and download to the FPGA board to make sure it is copied correctly Print all schematics to prepare for the final exam as described on slide 132 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Understand Critical Wires
RD : 4 bits The random digit DISP : 16 bits They represent the four position displays In Hex DISP15-DISP12 : the leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc NDISP : 16 bits New DISP bits NPDISP : 16 bits Display digits plus RD PDPRD : 4 bits Display overflow bits after addition CS 2204 Spring 2007 Experiment 6 Lab 10-14

Selplyr : 1 bit The current player If it is 0, it is the human player, otherwise, it is the machine player P1SEL : 4 bits The position played by the human player P2SEL : 4 bits The position played by the machine player PSEL : 4 bits Position Select bits of current player ENCPSEL : 2 bits The number of the position played CS 2204 Spring 2007 Experiment 6 Lab 10-14

BRWD : 4 bits Basic reward In Hex The digit played and minimum points earned Brwdeqz : 1 bit BRWD is zero when it is 1 EQ : 4 bits The equality of the four displays to the digit played NSD : 2 bits The number of similar digits, i.e. the adjacency information of the position played REGRWD : 8 bits The regular reward points calculated by only using adjacencies In Unsigned Binary RDRWD : 8 bits The random reward points generated from a freely running counter RWD : 8 bits The reward points earned by the play after adding REGRWD and RDRWD CS 2204 Spring 2007 Experiment 6 Lab 10-14

P1PT : 8 bits Player 1 points In BCD P2PT : 8 bits Player 2 points NPT : 8 bits New player points for the current player Ptovf : 1 bit The points overflow if it is 1, the new player points is above (255)10 CS 2204 Spring 2007 Experiment 6 Lab 10-14

P1add : 1 bit Player 1 adds when it is 1 P1rdrwd : 1 bit Player 1 requests a random reward when it is 1 P2add : 1 bit Player 2 adds when it is 1 P2rdrwd : 1 bit Player 2 requests a random reward when it is 1 Add : 1 bit The current player adds when it is 1 P1skip : 1 bit Player 1 skips when it is 1 P2skip : 1 bit Player 2 skips when it is 1 P1played : 1 bit Player 1 played when it is 1 P2played : 1 bit Player 2 played when it is 1 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Clear : 1 bit Clear FFs, registers, counters, etc. during reset in Block 2 and Block 4 so that it can play again Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers Clff : 1 bit Clears FFs in Block 2 so that the next player can play if there is no overflow Stp1pt : 1 bit Store Player 1 points Stp2pt : 1 bit Store Player 2 points Rdrwdsel : 1 bit Current player has requested a random reward when it is 1 Sysclk : 1 bit System clock of the operation diagram at 6 Hz to the digit played S1 : 1 bit State 1 where when it is 1, the Ppm is in state 1 S4 : 1 bit State 4 where when it is 1, the Ppm is in state 4 CS 2204 Spring 2007 Experiment 6 Lab 10-14

Project Manager Actions and Reminders
Make sure there is a CS2204 folder Make sure there is an experiment folder for the current experiment You can check the folder the current project is in by selecting File -> Project Info Make sure the FPGA chip and its model are correct when a new Xilinx project is created You can check the FPGA chip and its model by selecting File -> Project Type… The selections must be as follows The chip : Spartan The model : S10PC84 Speed : 3 CS 2204 Spring 2007 Experiment 6 Lab 10-14

If you copy a project completely and paste it as a new project, its schematic files cannot be worked on right away After you open the schematics, they are all Non-Project schematics Close all the schematics Close the schematics window Open the schematics one by one on the Project Manager window Double click on the schematic name on the upper left side for each schematic file CS 2204 Spring 2007 Experiment 6 Lab 10-14

When you do the first Xilinx IMPLEMENTATION or after clearing the implementation data, you need to change implementation options before clicking on “Run” in the Implement Design Window You can change the options by selecting Options… in the same window and then Increase the Place & Route Level to the Highest Effort on the “Options” window Click on the Edit Options… button for Implementation: in the Program Options area of the “Options” window Click on Place and Route on the “Spartan Implementation Options: Default” window Increase Router Options to 5 and 5 for both Routing Passes and Delay-Based Cleanup Passes CS 2204 Spring 2007 Experiment 6 Lab 10-14

After a successful IMPLEMENTATION The schematic files have a check mark next to them The Design Entry button will have a check mark The IMPLEMENTATION button has a check mark (after a delay of minutes sometimes) The PROGRAMMING button is highlighted If not, just click in anywhere in the Flow tab area of the Project Manager window, it will be highlighted If the IMPLEMENTATION is not successful due to errors, the IMPLEMENTATION button will have an “X” mark The error can be because of wrong chip selection or schematic design errors Correct them then ! CS 2204 Spring 2007 Experiment 6 Lab 10-14

After a Xilinx IMPLEMENTATION, read the Implementation Log File for errors, warnings and FPGA chip utilization You can read the Implementation Log File by selecting Reports -> Implementation Log File All No driver warnings must be corrected No Driver means, the wire is not connected to any component output All Multiple drivers warnings must be corrected Multiple Drivers means, a wire is connected to multiple component outputs Most No Load warnings can be ignored Because, the software warns that a component output is not used, because you do not need the output But, if a component output is needed, and not connected, then it is an error, the output must be connected to the input of a component CS 2204 Spring 2007 Experiment 6 Lab 10-14

After performing several Xilinx IMPLEMENTATIONs, clear the implementation data, by selecting Project -> Clear Implementation Data Back to back Xilinx IMPLEMENTATIONs use previous implementation data that is unchanged to save time Over time, this implementation data becomes corrupt and the bit file has errors Correct designs do not perform correctly on the FPGA board Clearing the implementation data changes the implementation options to the default ones The schematic files will keep their check marks The Design Entry button will keep its check mark But, the IMPLEMENTATION button will have a question mark The PROGRAMMING button will not be highlighted The implementation options must be changed to the required ones again CS 2204 Spring 2007 Experiment 6 Lab 10-14

Schematic Design Actions, Shortcuts & Reminders
Place team info on schematics You can enter the team info by selecting File -> Table Setup… Place your name & a partner name on Line1: Place names of the other two partners on Line 2: On Line3: place CS2204 – Section A/B/C/D/E/F – Spring 2007 Press F2 to enter the Select & Drag Mode Only, in this mode components can be deleted, rotated, copied and pasted You can press ESC to enter the Select & Drag Mode Press F3 to get component library on screen VCC is logic 1 GND is logic 0 To quickly locate a component, enter the first few letters of the component in the bottom area of the SC Symbols window To locate XOR gates, just enter letter “X” and “O” CS 2204 Spring 2007 Experiment 6 Lab 10-14

Press F4 to draw wires Press F5 to draw buses Press F7 to search for wires and components To search for wires, select the Signal/Bus mode If the wire does not have a name, the software assigns one that starts with a “$” symbol and ends with a “_” symbol Use the whole name to search for a wire To search for a component, select the Instance mode If a component does not have a name, the software assigns one that starts with “$I” symbols followed by a number Use the whole name to search for the component Press F8 to start simulation quickly Press F10 to refresh the screen CS 2204 Spring 2007 Experiment 6 Lab 10-14

Press ctrl-c to copy a wire or a component selected When components are copied, their labels are not copied ! You can copy from a schematic that belongs to another project To open the schematic of another project, click on button in the upper left corner, then select the schematic file which will be in another folder Press ctrl-v to paste a wire or a component Press ctrl-r/ctrl-l to rotate components right/left Wires cannot be rotated ! You can see how a Xilinx macro is designed (the internal structure), do a Hierarchy Push, by selecting Hierarchy -> Hierarchy Push You can close the macro internal design screen, by selecting Hierarchy -> Hierarchy Pop CS 2204 Spring 2007 Experiment 6 Lab 10-14

Unless otherwise stated, use Xilinx macros instead of designing them to save time Use buffers to rename wires Do not use unnecessary input/output buffers Do not use unnecessary input/output pads If you copy and paste components, their labels are not copied and pasted by the software You will need to “source” the schematic file to copy and paste component labels as explained in the Advanced Xilinx and Digilent Features handout Xilinx does not have high density ROM memory components 16x1-bit and 32x1-bit They may not be used at all If needed, its usage is described on page 9 of the Advanced Xilinx and Digilent Features handout CS 2204 Spring 2007 Experiment 6 Lab 10-14

Drawing buses by using Draw Buses button on the left side : Ppm buses are type None Individual wires of a bus must have names the same as the bus name The indices of individual wires start at 0 and are up to the number of bus wires minus 1 Bus NPT has 8 wires : NPT7, NPT6, NPT5,…, NPT1, NPT0 If a component generates a bus, there is no need to draw the individual wires of the bus, unless a components needs those individual wires CS 2204 Spring 2007 Experiment 6 Lab 10-14

Beautify the schematic for documentation purposes Place components of different sub/blocks separate from each other to recognize them Write Comments, draw lines and rectangles and label sub/blocks to identify them on the schematic for documentation purposes Use the Graphics Toolbox button on the left : Label components appropriately Wire names follow application and block partitioning naming requirements Except for wires that are connected IBUFs, OBUFs, IPADs and OPADs Component names start with a U Except if it is a BUF, IBUF, OBUF, IPAD or OPAD To label a component, right click on the component and select Symbol Properties… Give the name in the Reference: section of the Symbol Properties window CS 2204 Spring 2007 Experiment 6 Lab 10-14

Beautify the schematic for documentation purposes Do not leave components unused Draw short wires and label them with the same name To label wires double click on the wire and enter the name in the Net Name: area of the pop up window Draw wires without unnecessary turn Draw wires without tangling Draw wires around components/labels/names Do not short circuit input lines Do not short circuit output lines Do not have labels/attributes/components overlap CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform integrity tests to catch simple errors You can do an integrity test of the current schematic sheet, by selecting Options -> Integrity Test for Current Sheet After the completion, a window may tell you to look at the Project Manager window to read about warnings detected, even if it says the test passed successfully Look at the Project Manager window, you will see warnings in blue If the last line has the Schematic Contents OK line, there is no need to correct anything CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors Press F8 to start simulation quickly You will see the SC Probes window : To select the input wires to be simulated, click on the Stimulator tool button of the SC Probes windows : Then click on the input wires by precisely clicking on their names to select them There will be a square gray box shown on the left side of the input wire name Wires that have no name cannot be simulated, therefore, they must be given names for simulation When selecting input bus wires, click on the bus wires in the increasing index order : ABUS0, ABUS1, ABUS2,… CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors Press F8 to start simulation quickly You will see the SC Probes window : To select the output wires to be simulated, click on the Probe tool button of the SC Probes windows : Then click on the output wires by precisely clicking on their names to select them There will be a square gray box shown on the left side of the output wire name Wires that have no name cannot be simulated, therefore, they must be given names for simulation When selecting output bus wires, click on the bus wires in the increasing index order : OBUS0, OBUS1, OBUS2,… CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors Press F8 to start simulation quickly You will see the SC Probes window : To start the simulation, click on the Simulator button of the SC Probes window : Once you have the simulation window on the screen You will see the input wires listed and then the output wires on the left side of the Logic Simulator window CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors Separate the input rows from the output rows by placing a blank row between the input and output wires sets Click on the top output wire Make selections Signal -> Empty Rows -> Insert Combine bus bits to reduce the number of rows Click on the top bus wire which has the lowest index (ABUS0) Press shift and simultaneously click on the highest order bus wire (ABUS7) to select all the wires of the bus A turquoise rectangle covers the bus wires Right click on the turquoise rectangle and make the following selections Bus -> Combine CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors In order to simulate the circuit, the input wires must be first given new names Click on the Select Stimulators button : A keypad window will be shown Select an input wire by clicking on it (it will be covered by a turquoise rectangle) and then click on any letter key on the keypad, such as “q” To the right of the input wire, the new name “q” is shown To the right of “q”, the current value of the wire is shown ► If it is a single wire, the value is Hi-Z ◊ This has to be changed to have correct simulations ► If it is a bus, the value is shown as capital letter “Z” ◊ This has to be changed as well for correct simulations CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors To change the values of wires on the simulator window If it is a single wire, the value is Hi-Z : Just click on the Hi-Z line to make the value 0 ►The value is shown to the right of name “q” as 0 Click on the 0 value line again to make the value 1 ►The value is shown to the right of name “q” as 1 If it is a bus, the value is shown as capital letter “Z” Click on Logical States to give a value to the bus : ►The Stimulator State Selection window will be shown Click on the bus name, such as ABUS Enter an appropriate Hex value in the Bus State area, such as “FA” ► Appropriate means the Hex value must fit the width of the bus : “FA” implies, the bus has at least eight wires Click on the Bus button of the Stimulator State Selection window : ►The value assigned is shown to the right of name “q” as “FA” CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors To change the values of wires on the simulator window To have a clock signal as an input follow the steps below : Make sure the input signal is not renamed as “q”, “w” etc. Click on the input signal to select it Click on the Select Stimulators button : Click on Formula… Double click on C1: under Clocks Enter the following in the Edit Formula area : 100ns=H 100ns=L ► This means a periodic signal which is 100 ns 1 and 100 ns 0 is generated ► The periodic signal has a period of 200ns or a frequency of 5MHz Click Accept Click Close You will see the C1 button on the Select Stimulators window highlighted Click on C1 so that the input signal is renamed C1 Click on the Simulation Step button several times : You will see the periodic signal automatically generated and the output values in response to that CS 2204 Spring 2007 Experiment 6 Lab 10-14

Perform logic simulations to catch logic errors Start simulating the circuit for different input combinations If the circuit has 4 or less inputs, then simulate the circuit for all input combinations (test vectors) 16 or less number of input combinations (test vectors) If the circuit has more than 4 inputs, select a number of input combinations (test vectors) then simulate the circuit for these test vectors Which test vectors to choose is a very important task ! To simulate the circuit, click on the Simulation Step button several times : Observe the outputs If they are correct, try another input combination If wrong, return to the schematic and try to figure out why it is wrong ! If an output value is Hi-Z or Unknown, there is an error, correct it CS 2204 Spring 2007 Experiment 6 Lab 10-14

Printing schematics Double click on the Printer227 icon on your desktop and wait about a minute to allow it to affect the printing option Zoom into an area of the schematic to print the area Select File -> Print on the schematic window Change the option to Current View Only on the Print window Click on Setup on the Print Window Change the printer to HP Printer 8150 in Room 227 Click on Options to select Landscape printing if necessary Click OK as many times as needed to print the page Print one copy of each area and then make copies of the printed schematics for your partners CS 2204 Spring 2007 Experiment 6 Lab 10-14

What to do if the testing on the board gives wrong results even thought the design is correct ?
If the design is absolutely correct, here are the steps to follow in sequence : The FPGA board is turned on ? SW9 is in the PROG position ? The Bitronics Data Switch selects your PC ? The FPGA type and model are correct ? The implementation options are changed ? There are not too many levels of folders to reach the project on the PC ? Clear the implementation data, close the software, restart the software and do a new Xilinx IMPLEMENTATION Does it work now ? Save the schematic file worked on in a separate folder Delete the project, recreate the project, copy the schematic design from the saved schematic file Does it work ? Download the zipped project from the course web site, unzip it, copy the schematic design from the saved schematic file CS 2204 Spring 2007 Experiment 6 Lab 10-14

What to do if the testing on the board gives wrong results even thought the design is correct ?
Repeat step 7, by using your partner’s working schematic Login to another PC and try steps 5 - 8 Ask from the TA to help you The TA will login to your original PC and try steps 5 – 8 by using your schematic design and his/her S drive The TA will login to another PC and try steps 5 – 8 by using your schematic design and his/her S drive on the new PC The TA will inform the professor If the project works on the second PC, inform the lab supervisor, Mr. Keni Yip that the original PC has a problem CS 2204 Spring 2007 Experiment 6 Lab 10-14

CS 2204 Spring 2007 Experiment 6 Lab 10 Lab 11 Lab 12 Lab 13.

Similar presentations

Presentation on theme: "CS 2204 Spring 2007 Experiment 6 Lab 10 Lab 11 Lab 12 Lab 13."— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

CS 2204 Spring 2007 Experiment 6 Lab 10 Lab 11 Lab 12 Lab 13.

Similar presentations

Presentation on theme: "CS 2204 Spring 2007 Experiment 6 Lab 10 Lab 11 Lab 12 Lab 13."— Presentation transcript:

Similar presentations

About project

Feedback