1. Synchronous logical networks II
Digital Systems M

2. Direct synthesis (using DFFs, decoders etc)
Exercise
A logical network must implement a synchronous network based on a binary counter base 4 with synchronous EN and U/!D commands so that the output sequence is
(ripetitive)
Direct synthesis (using DFFs, decoders etc)
Formal Synthesis
001
000
010
100
011 00 01 10 11
101
110
111
Transition table
y3y2y1
z2z1
001
000
011
010
110 00 01 10 11
100
101
111
Another alternative transition table
Gray code
y3y2y1
z2z1
001,00
001,01
001,11
001,10 y3
y2y1 1 00 01 11 10
Karnaugh Map

3. State tables(to be completed..)
Cont x 4 Q1 Q0
U/D* EN
Dec 3
FFD Q
U/!D D M U X 1
SEL !Q
The FF switches only if EN=0
What network for EN ? ?
Starting from 00 with U/!D=1 the counter counts up keeping EN=1 until 11 is reached (DEC3), when EN becomes 0 and therefore at the next clock the counter doesn’t count while U/!D switches activating DOWN=1 [that is !(U/!D) = 1]. EN becomes then 1 and the counter counts down (as long as DOWN is 1) until 00 when the stall occurs again
State tables(to be completed..)
Q1 Q0 U/!D EN 1 ..
EN= DEC1+DEC2+ DEC3*!(U/!D)+DEC0*U/!D

4. Inversion enable and
counter block
Decoder
Counter
The value of base 4 counter CB2CLED is decoded and triggers a variation of FF1 (which selects the counter direction)) when 0 is reached if Down (3 if Up). The signal enabling the FF switch acting on the three ways MUX, inverted, is also the counter enable. Therefore when the counter direction inversion is enabled the counter is disabled

5. Behavioural simulation

6. Waveforms generation Q Clock 3T 2T Z Z T Clock Cx5
It is possble to generate periodical waveforms through synchronous circuits whose period is an integer submultiple of che clock period
Clock Q
Example 1: by 2 frequency divider
D0..k
Q0..k CK D !Q
Example 2: generation of a waveform with 5T period (T period of the clock) whose output is high for 3T and low for 2T
Q0 Q1 Q2 CK
Cx5 C B A 1 2 3 4 Z
Clock Z T 3T 2T
NB: a logical network can only implement frequency dividers and never frequency multipliers (which can be achieved only through non linear analog circuits)

7. What sort of circuit is this ?
D0..k
Q0..k CK D0
!Q0 D1
!Q1 D2
!Q2
Clock
NB: The clock signal is not the same for all FFs (7493)
Clock
!Q0
!Q1
!Q2
This is not a synchronous binary counter (it is called also an asynchronous counter). Its FFs do not use the same clock signal and this implies that among the FFs outputs a little disalignment takes place. This sort of circuit can’t be synthesized as a synchronous circuit and a formal synthesis can be achieved only by considering the circuit as asynchronous that is by “opening” the FFs. (How many states in this case ?)

8. How can a DFF catch a pulse shorter than a clock period ?
Type A monoimpulsor “revisited” D2 Q2
!Q2 CK
DFF Z
Clock D1 Q1
!Q1 D0 Q0
!Q0
“1” CL
Ths short pulse is «captured» by FF 0 (provided it is sufficiently wide for the FF technology) – which acts as an integrator – whose output is fed to the A type monoimpulsor. The output of FF1 resets the FF0 (if CL is “positive”true”).
Can a problem arise since the Clear is asynchronous?
NB:This circuits and the previous one underline the fact no network is intrinsically synchronous and that in general it is almost always necessary the use of circuits of different nature. This is in any case true because there are always interacting networks which use different clocks and input signals not mutually synchronous

9. Shift registers
A left (right) shift register is a register made of DFFs, which at each clock positive edge copies the value of its right ((left) FF. In the last FF on the right (left ) a “0” is copied. This type of shift register is called «logic shift register».
D0..k
Q0..k CK Dn Qn
Dn-1
Qn-1
Dn-2
Qn-2 D0 Q0
“1”
Left shift register
For the shift registers too there are many versions: parallel in serial output, serial input parallel output, with or without reset, load signals etc. etc.
A shift register is also a counter. If upon a reset the input of FF0 is kept to 1 the shift register is incrementally filled with «1»: the number of «1» (or the position of the leftmost 1) indicates the count value
Very often the same register can shift either left or right according to an input control signal. This is achieved inserting a 2-way Mux before each D input, whose inputs are the outputs of either the left or right FF (Qì+1 or Qì-1.). With this configuration the shift register becomes an Up/down counter

10. 3-bit right shift-register
OUT0
OUT1
OUT2
DFF
DFF
DFF IN D Q D Q D Q Q* Q* Q* R* R* R*
A_RESET*
A_RESET*
A_RESET* CK

11. CK IN A_RESET OUT2 OUT1 OUT0
3-bit shift-register CK IN
A_RESET
OUT2
OUT1
OUT0

12. Example: 74164 (serial IN-parallel OUT)
In this shift register, for each positive clock edge (CP) data are shifted one position right (Q0 -> Q1, Q1->Q2 etc). The register has a Master Reset (MR – negative true) and the bit inserted in Q0 FF is the AND of the two inputs Dsa e Ds
It must be noticed that the shift operation corresponds arithmetically (without sign) to the division and multiplication by 2. Suppose that in Q0 the MSbit is stored and in Q7 the LSbit
Shift left => x2
= 21210
Weight
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
L/R CK
= 10610
Shift right => /2
= 5310

13. Arithmetic Shift
There are also arithmetic shift registers. In these right shift registers instead of inserting a “0” in the most left FF the same logic value is always inserted Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 D7 D6 D5 D4 D3 D2 D1 D0 I LD CK
Example
2’s complement negative numbers
Arithmetic
Shift Right
= 5410
= 2710
The arithmetic right shift implements a division by 2 maintaining the sign !! Obviously the same holds for the positive numbers.

14. Rotation
In the computers it is often necessary to implement a right or left rotation of a register content. This is achieved by a feedback shift register
D0..k
Q0..k CK Dn Qn
Dn-1
Qn-1
Dn-2
Qn-2 D0 Q0
Very often the direction must be programmable In this case the input of D0 (through a MUX 2:1) can be Q1 or Qnand so on

15. Shift register counters
Shift register based counter through EX-OR feedback
3 bit shift right D Q0 Q1 Q2
100
110
111
011
101
010
001
000
Disjoint state diagram !!
A n FF shift register with an EX-OR feedback (with variable inputs selected) is a NON binary counter for 2n-1 (provided it is not preset with all zeros)

16. 000->100->110->111->011->001->000->….
Johnson Counter
FFD D Q Q* R*
A_RESET*
OUT2
OUT1
OUT0 CK
000->100->110->111->011->001->000->….
Disjoint states loop : 101->010->101..>
In general with n FF the disjoint states are those with alternate 0s and 1s1
A Johnson counter with N FFs counts for 2N. Since successive Johnson counter configurations differ by a single bit (adjacent configurations) it can be used for generating glitches-free waveforms

17. 0001->1000->0100->0010->0010
Single «1» ring counter (directly generating a 1 over n code)
FFD D Q Q* R*
RESET*
PR*
OUT3
OUT1
OUT0 CK
OUT2
0001->1000->0100->0010->0010
The ring counter needs N FFs in order to count for N (while with the binary counters the number of FF necessary for a N count is m= |log2N| that is the first integer greater or equal to log2N)

18. POST-ROUTE SIMULATION
Z output is delayed 10 ns from the clock positive edge because of the switch delay
Not valid input
Enable=0

19. Barrel shifter (rotor)
A barrel shifter is a shift register able to shift “n” positions in a single period its FFs contents. A-H inputs are synchronously stored in the FFs when the LDST is activated. When
LDST is 0 upon each clock positive edge an anticlockwise n-positions rotation takes place where n is the binary value of S0, S1 and S2 signals.
For instance if ” ” is rotated 4 positions at the first clock the content becomes “ ”. If then it is rotated 3 positions it becomes “ ”
It must be noticed that the component is a register with «n» 8:1 Muxs, each one connected to the D inputs of the FFs. The Mux control input value n is given by S0, S1 and S2.
Vivado Barrel shifter

20. The last six right signals are the true and inverted selection signals (S1, !S1, S2, !S2, S3 e !S3) for the 8:1 MUXs
Preset value
The circuit in figure is one of the eight 8:1 MUXs which select the values to be stored in the FFs
MUX
The first left 8 signals are the values of the FF D inputs in the preceding period
Each 8:1 MUX is ORed with preset input value which is used together with !LOAD (if LOAD=1 the OR preset value is 0). The FF output is ANDed with !LOAD: this zeroes all MUX outputs allowing the preset values to be stored in the FFs

21. EPROM based synchronous networks
Z0..m
X0..n
EPROM
Y0..k
y0..k
D0..k
D0..k
Q0..k
Q0..k CK CK
Clock
FFD0..k
Nowadays instead of the EPROMs the PLAs (Programmable Logical Arrays) are used, that is devices where the combinatorial functions are optimized (combinatorial functions implementations are not necessarily canonical). The basic principle is however the same.

22. RSS Exercise D P Enable V E
Design a synchronous logical network (SRL) able to detect palindrome 4 bit configurations (that is configurations that are identical when read left to right or viceversa) which are sequentially inserted in a shift register. The D input is significant (and therefore valid for the sequence) only when the input Enable is 1 (which is not necessarilly the case for four consecutive input bits). The output P is 1 for a single period when a palindrome configuration is detected after a 4 bit sequence is received. Then a new 4 bit sequence must be received (by E conditioned) and detected. Direct synthesis
RSS D V P
Enable E

23. This is the basic architecture of the central unit of any computer
Exercise
Design in Vivado a synchronous logical network which implements in sequence (after a START) signal the sum of two four bits absolute numbers (A and B) then 2’s complements the result, then exchanges the two MSBits with the two LSBits and eventually divides arythmetically the result by 2.
Example
A=1100 B=0101 => Sum 0001
Exchange => 0100 (410)
2’s complement => 1100 (-410)
Arithmetical division (right shift) by two => 1110 (-210)
This is the basic architecture of the central unit of any computer
The only difference is that for the computers instead of a fixed sequence of elementary operations a new different sequence is generated for each instruction which must be executed.

24. Exercise
The synchronous network of figure must add modulo 256 the 8 bit data received in parallel on lines D[7..0]. The sum must be updated each clock and presented on the output lines OUT[7..0]. In case the input data is 68H the sum must not be updated and the input data discarded. In addition whenever 6 significant data have been received (that is excluding 68H) the output signal F must be set for one clock period during the reception of the sixth data. A reset input is also available which zeroes the outputs and resets the data count. Direct and Vivado design
SSN
A_RES
D[7..0]
OUT[7..0] F
Clock

25. Exercise
A synchronous sequential network must monitor the data received on the 8 lines D[7..0]: the data received are significant only if ENSYS=1. The networks must count modulo 256 how many data are divisible by 4 while ENSYS=1 (excluding 0). The network has two more inputs THREE e RESET. The signal THREE when asserted indicates that the value for increasing the count (if the data is divisible by 4) must be 3 (on the contrary if THREE is 0 the count must be increased by 1). The synchronous RESET signal overrides all other signals. Direct and Vivado design.
RSS EN
U[7..0]
RESET
THREE
I[7..0]
SSN

26. Exercise
Design a synchronous sequential network which according to two programming bits X1 and X0 generates the following four output sequences of two bits (signals U1 and U0) which end always with 11:
if X1=0 e X0=0
if X1=0 e X0=1
if X1=1 e X0=0
if X1=1 e X0=1
The programming signals X1 and X0 are significant at the end of each sequence that is only when the output is 11. The network has a synchronous RESET. Direct and Vivado synthesis
RSS CK X1 X0 U1 U0

27. Exercise
Design (direct and Vivado design) a SSN which ininterruptedly checks and counts, according to the subsequently explained rules, whether the last 4 bits received on a serial input IN are either “1001” or “0110”. Whenever the “1001” is received, a module 16 counter must be incremented by 1, on the contrary if the sequence “0110”is received the counter must be decreased by 1. Upon all other sequences the counter status doesn’t change. If the counter status is no decrement in any case can take place. If the counter status is 1111 it must be incremented if the right sequence (“1001”) is received .
Design the combinatorial networks RC1 and RC2 which allows to check whether the last 4 received bits (B3, B2, B1, B) are “1001” or “0110”.
Design a module 16 counter (up-down) with U/!D and EN inputs using module 4 up/down counters with U/!D and EN.
The system must have an output Z signalling the overflow or the attempted underflow of the counter
RC1 B3 B2 B1 B0
RC2
Z1=1 if “1001”
Z2=1 if “0110”

28. Exercise Synchronous network
Design (direct and Vivado) a periodic rectangular waveform generator (T=5ns – frequency ?) with programmable duty-cycle (the percentage of a period where the signal is 11). The duty cycle is coded by two input signals I1 e I0 as follows:
I1I0 = 00 duty-cycle 10%
I1I0 = 01 duty-cycle 30%
I1I0 = 10 duty-cycle 50%
I1I0 = 11 duty-cycle 80%
I1 and I0 are meaningful only if the input signal SET is 1: in this case a new duty cycle is set starting from the next clock. The clock period is 500ps (frequency ?) . The system is based on a modulo 16 counter with ENABLE and synchronous RESET.
10%
30%
50%
80%
SET
Synchronous
network I1 Z I0 CK

29. Exercise Schematic and VHDL
A synchronous network must monitor the bits received on a serial input S so as to detect when within a group of three consecutive bits the binary value is less than 2 or greater than 5. The groups do not overlap and the bit are received starting from the MSbit. Upon the reception of the third bit a V bit is set indicating that a group has been received and the output Z for a period if the condition is met otherwise reset it: in all other periods the Z output is don’t care. Direct and Vivado synthesis
Schematic and VHDL

30. Exercise
A traffic light control triggers the shutter of a camera when vehicles cross the traffic stop (light) line with a red light. A synchronous network with two inputs T and X must be designed. T is the traffic light status: T=1 if the traffic light is red.
X is a synchronous signal which samples the presence of a vehicle over the traffic light line. The output Z controls the camera shutter which must be activated only when the vehicle has crossed completely the traffic light line with the red light. In order to obtain well focused pictures the shutter must be activated after one clock period if the vehicle crosses the line in one period and after two periods otherwise. It is assumed that the system clock is such that the sensor can in any case detect a vehicle and that the distance between two consecutive vehicles (X=0) is at least three che clock periods. Formal and Vivado synthesis.

31. Design a synchronous network with two synchronous inputs E and A and an output U lasting one clock period. A ist valid only if E is at the same time 1. The network output must be 1 for one clock when A is 1 for five times (non consecutive too). Whenever A is 0 the number of ones must be decremented by 1. When the value 0 is reached and A=0 (with E=1) the count in not decremented any more. After U=1 the network the count is reset. Direct synthesis.

32. The following network must be analysed
LOAD active only if EN=1

33. A given (not to be designed) logical network sends not continuously 4 bit data to network B. When network A has a new data stores them with the rising edge of its STORE signal (asynchronous) in a register F whose output is the input of B and waits for the B signal READY activation which states that the new data have been read. The network B upon reception the new data signal waits for 3 clock periods and on the third reads the input register with the new data which must be stored in its internal B register: concurrently the signal READY is activated which in turn allows A (when A is ready for it) to store new data in F. Direct design.

34. ? Exercise OUT OUT CK a_res CK OUT (0) (1) (2) (3) (0) (1) (2) (3)
Design with VHDL a synchronous logical network which periodically, after three clock periods, sets to 1 for one clock period its output. The network is provided with a reset signal (a_res). ?
OUT
OUT CK
a_res CK
OUT
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)