INPUT-OUTPUT ORGANIZATION

INPUT-OUTPUT ORGANIZATION
Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes of Transfer Priority Interrupt Direct Memory Access Input-Output Processor Serial Communication

PERIPHERAL DEVICES Input Devices Output Devices Keyboard
Optical input devices - Card Reader - Paper Tape Reader - Bar code reader - Digitizer - Optical Mark Reader Magnetic Input Devices - Magnetic Stripe Reader Screen Input Devices - Touch Screen - Light Pen - Mouse Analog Input Devices Card Puncher, Paper Tape Puncher CRT Printer (Impact, Ink Jet, Laser, Dot Matrix) Plotter Analog Voice

INPUT/OUTPUT INTERFACE
Input/Output Interfaces INPUT/OUTPUT INTERFACE Provides a method for transferring information between internal storage (such as memory and CPU registers) and external I/O devices Resolves the differences between the computer and peripheral devices Peripherals - Electromechanical Devices CPU or Memory - Electronic Device Data Transfer Rate Peripherals - Usually slower CPU or Memory - Usually faster than peripherals Some kinds of Synchronization mechanism may be needed Unit of Information Peripherals – Byte, Block, … CPU or Memory – Word Data representations may differ

I/O BUS AND INTERFACE MODULES
Input/Output Interfaces I/O BUS AND INTERFACE MODULES I/O bus Data Processor Address Control Interface Interface Interface Interface Keyboard and Magnetic Magnetic Printer display disk tape terminal Each peripheral has an interface module associated with it Interface - Decodes the device address (device code) - Decodes the commands (operation) - Provides signals for the peripheral controller - Synchronizes the data flow and supervises the transfer rate between peripheral and CPU or Memory Typical I/O instruction Op. code Device address Function code (Command)

CONNECTION OF I/O BUS Connection of I/O Bus to CPU CPU I/O bus
Input/Output Interfaces CONNECTION OF I/O BUS Connection of I/O Bus to CPU Computer Op. Device Function Accumulator code address code register I/O control CPU Sense lines Data lines I/O bus Function code lines Device address lines Connection of I/O Bus to One Interface Data lines Peripheral register Device address Buffer register Output peripheral I/O bus device AD = 1101 Interface Logic and controller Function code Command decoder Sense lines Status register

I/O BUS AND MEMORY BUS Functions of Buses
Input/Output Interfaces I/O BUS AND MEMORY BUS Functions of Buses * MEMORY BUS is for information transfers between CPU and the MM * I/O BUS is for information transfers between CPU and I/O devices through their I/O interface * Many computers use a common single bus system for both memory and I/O interface units - Use one common bus but separate control lines for each function - Use one common bus with common control lines for both functions * Some computer systems use two separate buses, one to communicate with memory and the other with I/O interfaces - Communication between CPU and all interface units is via a common I/O Bus - An interface connected to a peripheral device may have a number of data registers , a control register, and a status register - A command is passed to the peripheral by sending to the appropriate interface register - Function code and sense lines are not needed (Transfer of data, control, and status information is always via the common I/O Bus) Physical Organizations I/O Bus

ISOLATED vs MEMORY MAPPED I/O
Input/Output Interfaces ISOLATED vs MEMORY MAPPED I/O Isolated I/O - Separate I/O read/write control lines in addition to memory read/write control lines - Separate (isolated) memory and I/O address spaces - Distinct input and output instructions Memory-mapped I/O - A single set of read/write control lines (no distinction between memory and I/O transfer) - Memory and I/O addresses share the common address space -> reduces memory address range available - No specific input or output instruction -> The same memory reference instructions can be used for I/O transfers - Considerable flexibility in handling I/O operations

I/O INTERFACE I/O CPU Device Programmable Interface
Input/Output Interfaces I/O INTERFACE Port A I/O data register Bidirectional Bus data bus buffers Port B I/O data register I/O Device CPU Chip select CS Internal bus Register select RS1 Control Control Timing register Register select RS0 and Control I/O read RD Status Status I/O write WR register CS RS1 RS Register selected x x None - data bus in high-impedence Port A register Port B register Control register Status register Programmable Interface - Information in each port can be assigned a meaning depending on the mode of operation of the I/O device → Port A = Data; Port B = Command; Port C = Status - CPU initializes(loads) each port by transferring a byte to the Control Register → Allows CPU can define the mode of operation of each port → Programmable Port: By changing the bits in the control register, it is possible to change the interface characteristics

ASYNCHRONOUS DATA TRANSFER
Synchronous and Asynchronous Operations Asynchronous Data Transfer Synchronous - All devices derive the timing information from common clock line Asynchronous - No common clock Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted Two Asynchronous Data Transfer Methods Strobe pulse - A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur Handshaking - A control signal is accompanied with each data being transmitted to indicate the presence of data - The receiving unit responds with another control signal to acknowledge receipt of the data

Source-Initiated Strobe Destination-Initiated Strobe
Asynchronous Data Transfer STROBE CONTROL * Employs a single control line to time each transfer * The strobe may be activated by either the source or the destination unit Source-Initiated Strobe for Data Transfer Destination-Initiated Strobe for Data Transfer Block Diagram Block Diagram Data bus Data bus Source Destination Source Destination unit unit unit Strobe Strobe unit Timing Diagram Timing Diagram Valid data Valid data Data Data Strobe Strobe

HANDSHAKING Strobe Methods Source-Initiated
Asynchronous Data Transfer HANDSHAKING Strobe Methods Source-Initiated The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data Destination-Initiated The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Reply to the unit that initiates the transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE
Asynchronous Data Transfer SOURCE-INITIATED TRANSFER USING HANDSHAKE Data bus Block Diagram Source Data valid Destination unit Data accepted unit Valid data Timing Diagram Data bus Data valid Data accepted Sequence of Events Source unit Destination unit Place data on bus. Enable data valid. Accept data from bus. Enable data accepted Disable data valid. Invalidate data on bus. Disable data accepted. Ready to accept data (initial state). * Allows arbitrary delays from one state to the next * Permits each unit to respond at its own data transfer rate * The rate of transfer is determined by the slower unit

DESTINATION-INITIATED TRANSFER USING HANDSHAKE
Asynchronous Data Transfer DESTINATION-INITIATED TRANSFER USING HANDSHAKE Data bus Block Diagram Source Data valid Destination unit Ready for data unit Timing Diagram Ready for data Data valid Valid data Data bus Sequence of Events Source unit Destination unit Ready to accept data. Place data on bus. Enable ready for data. Enable data valid. Accept data from bus. Disable data valid. Disable ready for data. Invalidate data on bus (initial state). * Handshaking provides a high degree of flexibility and reliability because the successful completion of a data transfer relies on active participation by both units * If one unit is faulty, data transfer will not be completed -> Can be detected by means of a timeout mechanism

ASYNCHRONOUS SERIAL TRANSFER
Asynchronous Data Transfer ASYNCHRONOUS SERIAL TRANSFER Asynchronous serial transfer Synchronous serial transfer Asynchronous parallel transfer Synchronous parallel transfer Four Different Types of Transfer Asynchronous Serial Transfer - Employs special bits which are inserted at both ends of the character code - Each character consists of three parts; Start bit; Data bits; Stop bits. 1 1 1 1 Start Stop Character bits bit (1 bit) bits (at least 1 bit) A character can be detected by the receiver from the knowledge of 4 rules; - When data are not being sent, the line is kept in the 1-state (idle state) - The initiation of a character transmission is detected by a Start Bit , which is always a 0 - The character bits always follow the Start Bit - After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect

UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - UART -
Asynchronous Data Transfer UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - UART - A typical asynchronous communication interface available as an IC Transmit Bidirectional Transmitter Shift data data bus Bus register register buffers Control Transmitter Transmitter clock register control and clock Chip select CS Internal Bus Register select RS Timing Status Receiver Receiver CS RS Oper. Register selected x x None WR Transmitter register WR Control register RD Receiver register RD Status register register control clock I/O read and and clock RD Control I/O write Receive WR Receiver Shift data register register Transmitter Register - Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver - Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits - Used for I/O flags and for recording errors Control Register Bits - Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits

FIRST-IN-FIRST-OUT(FIFO) BUFFER
Asynchronous Data Transfer FIRST-IN-FIRST-OUT(FIFO) BUFFER * Input data and output data at two different rates * Output data are always in the same order in which the data entered the buffer. * Useful in some applications when data is transferred asynchronously 4 x 4 FIFO Buffer (4 4-bit registers Ri), 4 Control Registers(flip-flops Fi, associated with each Ri) R1 R2 R3 R4 Data 4-bit 4-bit 4-bit 4-bit Data input register register register register output Clock Clock Clock Clock Insert S F 1 S F F 2 S S F F 3 S S F 4 Output ready R F' R F F' 1 2 R R F' F' 3 R R F' 4 Delete Input ready Master clear

MODES OF TRANSFER - PROGRAM-CONTROLLED I/O -
3 different Data Transfer Modes between the central computer(CPU or Memory) and peripherals; Program-Controlled I/O Interrupt-Initiated I/O Direct Memory Access (DMA) Program-Controlled I/O(Input Dev to CPU) Data bus Interface I/O bus Address bus Data register Data valid I/O CPU I/O read device I/O write Status Data accepted F register Read status register Check flag bit Polling or Status Checking = 0 flag Continuous CPU involvement CPU slowed down to I/O speed Simple Least hardware = 1 Read data register Transfer data to memory no Operation Polling, or polled operation, in computer science, refers to actively sampling the status of an external device by a client program as a synchronous activity. Polling is most often used in terms of input/output (I/O), and is also referred to as polled I/O or software driven I/O. complete? yes Continue with program

MODES OF TRANSFER - INTERRUPT INITIATED I/O & DMA
- Polling takes valuable CPU time - Open communication only when some data has to be passed -> Interrupt. - I/O interface, instead of the CPU, monitors the I/O device - When the interface determines that the I/O device is ready for data transfer, it generates an Interrupt Request to the CPU - Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing DMA (Direct Memory Access) - Large blocks of data transferred at a high speed to or from high speed devices, magnetic drums, disks, tapes, etc. - DMA controller Interface that provides I/O transfer of data directly to and from the memory and the I/O device - CPU initializes the DMA controller by sending a memory address and the number of words to be transferred - Actual transfer of data is done directly between the device and memory through DMA controller -> Freeing CPU for other tasks

PRIORITY INTERRUPT Priority
- Determines which interrupt is to be served first when two or more requests are made simultaneously - Also determines which interrupts are permitted to interrupt the computer while another is being serviced - Higher priority interrupts can make requests while servicing a lower priority interrupt Priority Interrupt by Software(Polling) - Priority is established by the order of polling the devices(interrupt sources) - Flexible since it is established by software - Low cost since it needs a very little hardware - Very slow Priority Interrupt by Hardware - Require a priority interrupt manager which accepts all the interrupt requests to determine the highest priority request - Fast since identification of the highest priority interrupt request is identified by the hardware - Fast since each interrupt source has its own interrupt vector to access directly to its own service routine

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -
Processor data bus VAD 1 VAD 2 VAD 3 * Serial hardware priority function * Interrupt Request Line - Single common line * Interrupt Acknowledge Line - Daisy-Chain Device 1 Device 2 Device 3 PI PO PI PO PI PO To next device Interrupt request INT CPU Interrupt acknowledge INTACK Interrupt Request from any device(>=1) -> CPU responds by INTACK <- 1 -> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device One stage of the daisy chain priority arrangement S R Q Interrupt request from device PI Priority in RF Delay Vector address VAD PO Priority out Interrupt request to CPU Enable PI RF PO Enable

PARALLEL PRIORITY INTERRUPT
Mask register INTACK from CPU Priority encoder I 1 2 3 y x IST IEN Disk Printer Reader Keyboard Interrupt register Enable Interrupt to CPU VAD Bus Buffer IEN: Set or Clear by instructions ION or IOF IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD generated by the Priority Logic Interrupt Register: - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instruction Mask Register: - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction

INTERRUPT PRIORITY ENCODER
Priority Interrupt INTERRUPT PRIORITY ENCODER Determines the highest priority interrupt when more than one interrupts take place Priority Encoder Truth table Inputs Outputs I0 I1 I2 I3 x y IST Boolean functions 1 d d d d d d x = I0' I1' y = I0' I1 + I0’ I2’ d d 0 (IST) = I0 + I1 + I2 + I3

INTERRUPT CYCLE At the end of each Instruction cycle
Priority Interrupt INTERRUPT CYCLE At the end of each Instruction cycle - CPU checks IEN and IST - If IEN  IST = 1, CPU -> Interrupt Cycle SP SP - 1 Decrement stack pointer M[SP]  PC Push PC into stack INTACK  1 Enable interrupt acknowledge PC  VAD Transfer vector address to PC IEN  Disable further interrupts Go To Fetch to execute the first instruction in the interrupt service routine

INTERRUPT SERVICE ROUTINE
Priority Interrupt INTERRUPT SERVICE ROUTINE address Memory I/O service programs 7 JMP DISK DISK Program to service 1 JMP PTR magnetic disk VAD= 3 2 JMP RDR PTR Program to service 3 JMP KBD line printer 8 Main program KBD interrupt 1 RDR Program to service 749 current instr. 750 character reader 4 KBD Stack Program to service 11 keyboard 5 2 255 256 256 Disk interrupt 750 6 9 10 Initial and Final Operations Each interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system Initial Sequence [1] Clear lower level Mask reg. bits [2] IST <- 0 [3] Save contents of CPU registers [4] IEN <- 1 [5] Go to Interrupt Service Routine Final Sequence [1] IEN <- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg. bits [5] Restore return address, IEN <- 1

Direct Memory Access DIRECT MEMORY ACCESS * Block of data transfer from high speed devices, Drum, Disk, Tape * DMA controller - Interface which allows I/O transfer directly between Memory and Device, freeing CPU for other tasks * CPU initializes DMA Controller by sending memory address and the block size(number of words) CPU bus signals for DMA transfer ABUS Address bus High-impedence (disabled) when BG is enabled Bus request BR DBUS Data bus CPU Bus granted BG RD Read WR Write Block diagram of DMA controller Address bus Data bus Data bus Address bus buffers buffers DMA select DS Address register Register select RS Internal Bus Read RD Word count register Control Write WR logic Bus request BR Control register Bus grant BG Interrupt Interrupt DMA request DMA acknowledge to I/O device

DMA I/O OPERATION Starting an I/O - CPU executes instruction to
Direct Memory Access DMA I/O OPERATION Starting an I/O - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command Upon receiving a GO Command DMA performs I/O operation as follows independently from CPU Input [1] Input Device <- R (Read control signal) [2] Buffer(DMA Controller) <- Input Byte; and assembles the byte into a word until word is full [4] M <- memory address, W(Write control signal) [5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1 [6] If WC = 0, then Interrupt to acknowledge done, else go to [1] Output [1] M <- M Address, R M Address R <- M Address R + 1, WC <- WC - 1 [2] Disassemble the word [3] Buffer <- One byte; Output Device <- W, for all disassembled bytes [4] If WC = 0, then Interrupt to acknowledge done, else go to [1]

Direct Memory Access CYCLE STEALING While DMA I/O takes place, CPU is also executing instructions DMA Controller and CPU both access Memory -> Memory Access Conflict Memory Bus Controller - Coordinating the activities of all devices requesting memory access - Priority System Memory accesses by CPU and DMA Controller are interwoven, with the top priority given to DMA Controller -> Cycle Stealing Cycle Steal - CPU is usually much faster than I/O(DMA), thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles, CPU remains idle - For those slow CPU, DMA Controller may steal most of the memory cycles which may cause CPU remain idle long time

DMA TRANSFER Direct Memory Access Interrupt Random-access BG CPU
memory unit (RAM) BR RD WR Addr Data RD WR Addr Data Read control Write control Data bus Address bus Address select RD WR Addr Data DMA ack. DS RS I/O DMA Peripheral BR Controller device BG DMA request Interrupt

INPUT/OUTPUT PROCESSOR - CHANNEL -
- Processor with direct memory access capability that communicates with I/O devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the I/O devices and perform data transfer operations - CPU initiates the channel by executing an channel I/O class instruction and once initiated, channel operates independently of the CPU Central processing unit (CPU) Peripheral devices Memory Memory Bus unit PD PD PD PD Input-output processor I/O bus (IOP)

CHANNEL / CPU COMMUNICATION
Input/Output Processor CHANNEL / CPU COMMUNICATION CPU operations IOP operations Send instruction to test IOP.path Transfer status word to memory If status OK, then send start I/O instruction to IOP. Access memory for IOP program CPU continues with another program Conduct I/O transfers using DMA; Prepare status report. I/O transfer completed; Interrupt CPU Request IOP status Transfer status word Check status word to memory location for correct transfer. Continue

Serial Communication A data communication processor is an I/O processor that distributes and collects data from many remote terminals connected through telephone and other communication lines. It is a specialized I/O processor designed to communicate directly with data communication networks. A communication network may consist of any of a wide variety of devices, such as printers, interactive display devices, digital sensors, or a remote computing facility. With the use of a data communication processor, the computer can service fragments of each network demand in an interspersed manner and thus have the apparent behavior of serving many users at once. In this way the computer is able to operate efficiently in a time-sharing environment.

I/O processor Vs data communication processor
The main difference between an I/O processor and a data communication processor is in the way the processor communicates with the I/O devices. An I/O processor communicates with the peripherals through a common I/O bus that is comprised of many data and control lines. All peripherals share the common bus and use it to transfer information to and from the I/O processor. A data communication processor communicates with each terminal through a single pair of wires. Both data and control information are transferred in a serial fashion with the result that the transfer rate is much slower. The task of the data communication processor is to transmit and collect digital information to and from each terminal, determine if the information is data or control and respond to all requests according to predetermined established procedures. The processor, obviously, must also communicate, with the CPU and memory in the same manner as any I/O processor.

I/O processor Vs data communication processor –cont’d
The way that remote terminals are connected to a data communication processor is via telephone lines or other public or private communication facilities. Since telephone lines were originally designed for voice communication and computers communicate in terms of digital signals, some form of conversion must be used. The converters are called data sets, acoustic couplers or modems (from "modulator-demodulator"). A modem converts digital signals into audio tones to be transmitted over telephone lines and also converts audio tones from the line to digital signals for machine use.

Synchronous transmission
Synchronous transmission does not use start-stop bits to frame characters and therefore makes more efficient use of the communication link. High-speed devices use synchronous transmission to realize this efficiency. The modems used in synchronous transmission have internal clocks that are set to the frequency that bits are being transmitted in the communication line. For proper operation, it is required that the clocks in the transmitter and receiver modems remain synchronized at all times. The communication line, however, contains only the data bits from which the clock information must be extracted. Frequency synchronization is achieved by the receiving modem from the signal transitions that occur in the received data. Any frequency shift that may occur between the transmitter and receiver clocks is continuously adjusted by maintaining the receiver clock 'at the frequency of the incoming bit stream. The modem transfers the received data together with the clock to the interface unit.

Asynchronous transmission
Contrary to asynchronous transmission, where each character can be sent separately with its own start and stop bits, synchronous transmission must send a continuous message in order to maintain synchronism. The message consists of a group of bits transmitted sequentially as a block of data. The entire block is transmitted with special control characters at the beginning and end of the block. The control characters at the beginning of the block supply the information needed to separate the incoming bits into individual characters.

Synchronous transmission
In synchronous transmission, where an entire block of characters is transmitted, each character has a parity bit for the receiver to check. After the entire block is sent, the transmitter sends one more character as a parity over the length of the message. This character is called a longitudinal redundancy check (LRC) and is the accumulation of the exclusive-OR of all transmitted characters. The receiving station calculates the LRC as it receives characters and compares it with the transmitted LRC. The calculated and received LRC should be equal for error-free messages. If the receiver finds an error in the transmitted block, it informs the sender to retransmit the same block once again. Another method used for checking errors in transmission is the cyclic redundancy check (CRC). This is a polynomial code obtained from the message bits by passing them through a feedback shift register containing a number of exclusive-OR gates. This type of code is suitable for detecting burst errors occurring in the communication channel.

Three different modes of data transmission
Data can be transmitted between two points in three different modes: 1. Simplex 2. Half-duplex & 3. Full-duplex

3 MODES- Simplex line A simplex line carries information in one direction only. This mode is seldom used in data communication because the receiver cannot communicate with the transmitter to indicate the occurrence of errors. Examples of simplex transmission : Radio and television broadcasting

3 MODES- Half-duplex transmission
A half-duplex transmission system is one that is capable of transmitting in both directions but data can be transmitted in only one direction at a time. A pair of wires is needed for this mode.

3 MODES- Full-duplex transmission
A full-duplex transmission can send and receive data in both directions simultaneously. This can be achieved by means of a four-wire link, with a different pair of wires dedicated to each direction of transmission.

Data link protocol The purpose of a data link protocol is
The communication lines, modems, and other equipment used in the transmission of information between two or more stations is called a data link. The orderly transfer of information in a data link is accomplished by means of a protocol. A data link control protocol is a set of rules that are followed by interconnecting computers and terminals to ensure the orderly transfer of information. The purpose of a data link protocol is to establish and terminate a connection between two stations, to identify the sender and receiver, to ensure that all messages are passed correctly without errors, and to handle all control functions involved in a sequence of data transfers.

PROTOCOL TYPES Protocols are divided into two major categories according to the message-framing, technique used. These are 1. Character-oriented protocol and 2. Bit-oriented protocol.

Character-Oriented Protocol
The character-oriented protocol is based on a character set. The code most commonly used is ASCII (American Standard Code for Information Interchange). It is a 7-bit code with an eighth bit used for parity. The code has 128 characters, of which 95 are graphic characters and 33 are control characters. The graphic characters include the upperand lowercase letters, the ten numerals, and a variety of special symbols. A list of the ASCII characters can be found in Table 6.8. The control characters are used for the purpose of routing data, arranging the test in a desired format, and for the layout of the printed page. The characters that control the transmission are called communication control characters. These characters are listed in Table 6.8. Each character has a 7-bit code and is referred to by a three-letter symbol. The role of each character in the control of data transmission is stated briefly in the function column of the table. The SYN character serves as synchronizing agent between the transmitter and receiver.

Character-Oriented Protocol- Cont’d.

When the 7-bit ASCII code is used with an odd-parity bit in the most significant position, the assigned SYN character has the 8-bit code which has the property that, upon circular shifting, it repeats itself only after a full 8-bit cycle. When the transmitter starts sending 8-bit characters, it sends a few characters first and then sends the actual message. The initial continuous string of bits accepted by the receiver is checked for a SYN character. In other words, with each clock pulse, the receiver checks the last eight bits received. If they do not match the bits of the SYN character, the receiver accepts the next bit, rejects the previous high-order bit, and again checks the last eight bits received for a SYN character. This is repeated after each clock pulse and bit received until a SYN character is recognized.

Once a SYN character is detected, the receiver has framed a character. From here on the receiver counts every eight bits and accepts them as a single character. Usually, the receiver checks two consecutive SYN characters to remove any doubt that the first did not occur as a result of a noise signal on the line. Moreover, when the transmitter is idle and does not have any message characters to send, it sends a continuous string of SYN characters. The receiver recognizes these characters as a condition for synchronizing the line and goes into a synchronous idle state. In this state, the two units maintain bit and character synchronism even though no meaningful information is communicated.

We transmit messages through the data link with an established format consisting of a header field, a text field, and an error-checking field. A typical message format for a character-oriented protocol is shown in Fig The two SYN characters assure proper synchronization at the start of the message. Following the SYN characters is the header, which starts with an SOH (start of heading) character. The header consists of address and control information. The STX character terminates the header and signifies the beginning of the text transmission.

The text portion of the message is variable in length and may contain any ASCII characters except the communication control characters. The text field is terminated with the ETX character. The last field is a block check character (BCC) used for error checking. It is usually either a longitudinal redundancy check (LRC) or a cyclic redundancy check (CRC). The receiver accepts the message and calculates its own BCC. If the BCC transmitted does not agree with the BCC calculated by the receiver, the receiver responds with a negative acknowledge (NAK) character. The message is then retransmitted and checked again. Retransmission will be typically attempted several times before it is assumed that the line is faulty. When the transmitted BCC matches the one calculated by the receiver, the response is a positive acknowledgment using the ACK character.

Bit-Oriented Protocol
This protocol does not use characters in its control field and is independent of any particular code. It allows the transmission of serial bit stream of any length without the implication of character boundaries. Messages are organized in a specific format called a frame. In addition to the information field, a frame contains address, control, and error-checking fields. The frame boundaries are determined from a special 8-bit number called a flag . Examples of bit-oriented protocols are: 1. SDLC (synchronous data link control) used by IBM, HDLC (high-level data link control) adopted by the International Standards Organization, and 2. ADCCP (advanced data communication control procedure) adopted by the American National Standards Institute

Bit-Oriented Protocol- Cont’d.
Any data communication link involves at least two participating stations. The station that has responsibility for the data link and issues the commands to control the link is called the primary station. The other station is a secondary station. Bit-oriented protocols assume the presence of one primary station and one or more secondary stations. All communication on the data link is from the primary station to one or more secondary stations, or from a secondary station to the primary station.

Bit-Oriented Protocol- Cont’d.
The frame format for the bit-oriented protocol is shown in Fig A frame starts with-the 8-bit flag followed by an address and control sequence. The information field is not restricted in format or content and can be of any length. The frame check field is a CRC (cyclic redundancy check sequence used for detecting errors in transmission. The ending flag indicate; to the receiving station that the 16 bits just received constitute the CRC bits The ending frame can be followed by another frame, another flag, or a sequence of consecutive Vs. When two frames follow each other, the intervening flag is simultaneously the ending flag of the first frame and the beginning flag of the next frame

Bit-Oriented Protocol- Cont’d
If no information is exchanged, the transmitter sends a series of flags to keep the line in the active state. The line is said to be in the idle state with the occurrence of 15 or more consecutive l's. Frames with certain control messages are sent without an information field. A frame must have a minimum of 32 bits between two flags to accommodate the address, control, and frame check fields. The maximum length depends on the condition of the communication channel and its ability to transmit long messages error-free.

To prevent a flag from occurring in the middle of a frame, the bit-oriented protocol uses a method called zero insertion. It requires a 0 be inserted by the transmitting station after any succession of five continuous l's. The receiver always removes a 0 that follows a succession of five l's. Thus the bit pattern is transmitted as and restored by the receiver to it original value by removal of the 0 following the five l's. As a consequence, no pattern of is ever transmitted between the beginning and ending flags.

Following the flag is the address field, which is used by the primary station to designate the secondary station address. An address field of eight bits can specify up to 256 addresses. Some bit-oriented protocols permit the use of an extended address field. To do this, the least significant bit of an address byte is set too if another address byte follows. A 1 in the least significant bit of a byte is use to recognize the last address byte.

The control field comes in three different formats, as shown in Fig

INPUT-OUTPUT ORGANIZATION

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