1. EEL 3705 / 3705L Digital Logic Design
Fall 2006 Instructor: Dr. Michael Frank
Lecture Module #7: Lab #2 Prep & Karnaugh Maps
9/17/2018
M. Frank, EEL3705 Digital Logic, Spring 2007

2. Topics for Today (Wed. 1/24)
Administrivia:
Don’t forget, “Reading Assignment #1” is due Tuesday.
Turn in your lab report from lab #1 in this week’s labs.
Lab #2 pre-lab report is due in lab starting next Tuesday.
Use lab time this week to catch up & get an early start on lab #2.
YOU ARE REQUIRED TO ATTEND THIS WEEK’S LABS!
A HW#1 will hopefully be posted shortly!
Homeworks are generally due 1 week after they are assigned.
Today’s Lecture:
Lab #2 preparation
Combinational logic synthesis example
Schematic entry, more on simulation
Common subexpression elimination
Further logic optimization using Karnaugh maps
Postponed to Fri. or Mon.:
Radix (Base) Conversion Techniques
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M. Frank, EEL3705 Digital Logic, Spring 2007

3. Example Logic Synthesis Problem
Design an efficient logic circuit that will, for any input integer n in the range 2-15, output the largest integer k<n such that k divides n (with no remainder).
To solve such a problem, first, design and describe an explicit representation of the input-output relation as a Boolean function,
and then synthesize and optimize a combinational circuit to compute the desired function.
Typical steps in such a process:
Design input interface specifications
Design output interface specifications
Design functional specifications (truth table)
Synthesize the logic
Optimize the logic
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M. Frank, EEL3705 Digital Logic, Spring 2007

4. Design Functional Specifications
Start by tabulating the input-output relation: n k 2 3 4 5 6 7 8 n k 9 10 11 12 13 14 15 1 3 1 5 2 1 1 6 3 1 1 7 4 5
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5. M. Frank, EEL3705 Digital Logic, Spring 2007
Design Input Encoding
How many input bits are needed, if we wish to be able to uniquely encode any one of the allowed input values?
What names shall we give to the different input bits?
How will each of the individual input values be represented as a list of values of those bits?
Are there any possible lists of input bit-values that do not correspond to any of the legal input values?
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M. Frank, EEL3705 Digital Logic, Spring 2007

6. Design Output Encoding
How many different possible output values are there?
What is the minimum number of bits required to uniquely represent each possible output?
Name the output bits.
How will the particular outputs be encoded?
There are seven of them: {1, 2, 3, 4, 5, 6, 7}.
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M. Frank, EEL3705 Digital Logic, Spring 2007

7. M. Frank, EEL3705 Digital Logic, Spring 2007
Next steps…
Write down the complete truth table…
Use “don’t care’s” as appropriate.
Commonly seen notations: “-”, “d”, or “x”
For each 1-bit Boolean function (output column),
synthesize a sum-of-minterms or product-of-maxterms expression for the function
Finally, simplify these expressions using any of several techniques…
Common subexpression elimination
Combining logically adjacent terms (K-maps help here)
many other manipulations are generally possible
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M. Frank, EEL3705 Digital Logic, Spring 2007

8. Today’s Lecture (Fri. 1/26)
New announcements:
If your TA gave you approval to submit late or revise your lab #1 report or pre-lab report, complete this by midnight Monday.
Turn in online through assignment link on Blackboard.
This is a final deadline, since I will be posting a Lab 1 report example early Tuesday.
So you can see it before turning in pre-lab 2.
Today’s Lecture:
Continue lab #2 preparation:
Review combinational logic synthesis example from last time
Schematic entry tips: Bussed wires, logic-gate megafunctions
Combining logically adjacent terms using Karnaugh maps
Postponed to Monday:
How to build a hierarchical design in Quartus
More K-map examples?
Radix (Base) Conversion Techniques
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M. Frank, EEL3705 Digital Logic, Spring 2007

9. Complete the Functional Specification
Inputs
Outputs #
Binary encoding
Binary enc. n n3 n2 n1 n0 k k2 k1 k0 d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Write out the truth table…
Here, we’re using “d” to mean “don’t care”
I.e., any output value is acceptable
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M. Frank, EEL3705 Digital Logic, Spring 2007

10. Compose the SoP/PoS Formulas
Sum-of-products / product-of-sums
Generally speaking,
If there are few 1’s, then SoP will be simpler
If there are few 0’s, then PoS will be simpler
For this problem:
k2 – 5 ones, 9 zeros – Try SoP
k1 – 5 ones, 9 zeros – Try SoP
k0 – 11 ones, 3 zeros – Try PoS
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M. Frank, EEL3705 Digital Logic, Spring 2007

11. M. Frank, EEL3705 Digital Logic, Spring 2007
SoP/PoS Formulas
Here, each term is annotated above with its propositional meaning:
n = 8
n = 10
n = 12
n = 14
n = 15
n = 4
n = 6
n = 9
n = 12
n = 14
n ≠ 4
n ≠ 8
n ≠ 12
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M. Frank, EEL3705 Digital Logic, Spring 2007

12. Circuit Corresponding to Equation for k0
One problem with this approach:
Gates with large numbers of inputs tend to be large (costly) and slow!
Thus, this approach does not scale well to functions with very large numbers of variables and terms.
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13. Techniques for Combinational Logic Optimization
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M. Frank, EEL3705 Digital Logic, Spring 2007

14. Goals of Circuit Minimization
(1) Minimize the number of primitive Boolean logic gates needed to implement the circuit.
Ultimately, this also roughly minimizes the number of transistors, the chip area, and the cost.
Also roughly minimizes the energy expenditure
among traditional irreversible circuits.
This will be our focus.
(2) It is also often useful to minimize the number of combinational stages or logical depth of the circuit.
This roughly minimizes the delay or latency through the circuit, the time between input and output.
Note: Goals (1) and (2) are often conflicting!
In the real world, a designer may have to analyze and optimize some complex trade-off between logic complexity and latency.
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M. Frank, EEL3705 Digital Logic, Spring 2007

15. M. Frank, EEL3705 Digital Logic, Spring 2007
Minimizing Circuits
Subtopics:
Combining logically adjacent terms using Karnaugh Maps (CIO #5)
Focus of this lecture
Don’t care conditions
Common subexpression elimination
The Quine-McCluskey Method
Optional; not covering this semester
Simplification using arbitrary Boolean identities
Not covering in depth this semester in lecture
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M. Frank, EEL3705 Digital Logic, Spring 2007

16. Minimizing DNF Expressions
Using DNF (or CNF) expressions guarantees that you can always find some circuit that implements any desired Boolean function.
However, the resulting circuit may be larger than is really required!
We would generally like to find the smallest sum-of-products expression that is equivalent to a given function.
This will yield a fairly small circuit.
However, circuits of other forms (not either CNF or DNF) might be even smaller for complex functions.
In general, finding the absolute smallest circuit is an NP-hard problem – not tractable for very complex functions
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M. Frank, EEL3705 Digital Logic, Spring 2007

17. Logic Simplification Technique #1: Common Subexpression Elimination
One general way to simplify any kind of algebraic expression is by combining repeated subexpressions
So they will only be computed once
Example: Consider the expression for k2
Some repeated subexpressions are indentified below
We can then create these “temporary variables:”
And then substitute them into the k2 expression:
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18. Equation with Common Subexpressions Combined, Rendered as a Circuit
Reduced width of AND gates, but now we need two levels of them…
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19. Logic Simplification Technique #2: Combining Logically Adjacent Terms
We can eliminate terms from SoP formulas using the Boolean identity:
So, any two product terms that differ only in the form (complemented or uncomplemented) of a single literal can be combined together,
while eliminating that literal from them!
This reduces both the number of terms, and the size of each term!
It is a big win.
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M. Frank, EEL3705 Digital Logic, Spring 2007

20. M. Frank, EEL3705 Digital Logic, Spring 2007
Lecture of Mon., 1/29/07
Announcements:
Any late or revised lab #1 reports must be submitted online tonight, no exceptions!
An example “perfect” report will be posted tomorrow at 6 AM.
Pre-lab reports for lab 2 are due at the start of your lab section this coming week (Tue.-next Mon.)
Today’s Lecture:
Continue lab #2 preparation:
Continue with Karnaugh map examples
How to build a hierarchical design in Quartus
Grouping signals for simulation
Postponed to Wed.:
Radix (Base) Conversion Techniques
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M. Frank, EEL3705 Digital Logic, Spring 2007

21. Example of Combining Logically Adjacent Terms in Formula for k2
(Play the slide to see the order of steps.)
n  {8, 10, 12, 14}
n  {14, 15}
case n=14 is covered twice, but this does not matter!
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M. Frank, EEL3705 Digital Logic, Spring 2007

22. Let’s now see how to speed up the simplification process using K-maps
To the right is the truth table again for just the one output bit k2
We’ll now see how to use it to quickly combine logically adjacent terms using a Karnaugh map
This is one of the official course objectives! It will be tested on exams! #
Input bits k2 n n3 n2 n1 n0 d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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23. M. Frank, EEL3705 Digital Logic, Spring 2007
K-map for k2 example
n1=0
n1=1
Prime implicants (PIs, circled) are maximal-sized groupings of 1’s
Can’t be further doubled w/o including zeros
PIs correspond to the simplest product terms
w the most variables eliminated
Essential prime implicants (EPIs, red) are PIs that cover 1s that no other PIs cover
These PIs must be included in your cover.
n1n0 n3n2 00 01 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 d d
n3=0
n2=1 1 1 1
n3=1 1 1
n0=1
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M. Frank, EEL3705 Digital Logic, Spring 2007

24. Circuit for Simplified k2 Equation
Structure corresponds directly to simplified formula…
Uses just one 2-input AND, one 3-input AND (inputs drawn as a bus), and one 2-input OR.
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M. Frank, EEL3705 Digital Logic, Spring 2007

25. Top-Level Block Diagram for Divisor-Finding Circuit, So Far
Symbols for subcircuits we already created
Should pass Analysis but not Synthesis (since divisor1 block has not been functionally defined, to Quartus, it cannot be synthesized)
bus line
signal conduit
Block – placeholder in schematic for subcircuit not yet designed
node line
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26. Truth Table and K-map for k1#
Input bits k1 n n3 n2 n1 n0 d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
n1n0 n3n2 00 01 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 d d
n3=0 1 1
n2=1 1 1
n3=1 1
n0=1
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27. Optimized SoP circuit for k1
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28. Truth Table and PoS K-map for k0#
Input bits k0 n n3 n2 n1 n0 d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
n1n0 n3n2 00 01 11 10 1 3 2 4 5 7 6 12 13 15 14 8 9 d d 1 1
n3=0 1 1 1
n2=1 1 1 1
n3=1 1 1 1
n0=1
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29. Optimized PoS circuit for k0
The big circuit on slide 12 has been simplified to a single OR gate!
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30. Completed Top-Level Schematic
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31. Another Possible Top-Level Design
Instead of dividing up the design by output bits,
we could have divided it up into the first and second levels of gates…
AND gates for k2 minterms and k1 minterms go in here
OR gates for combining minterms 4
div2
num3..0
Minterm generator 4
Minterm combiner
div1
div3..0
Maxterm generator
Maxterm combiner
div0
Not needed in our example – no negated literals in maxterms
The single OR gate for k0 goes in here
AND gates for combining maxterms (none in this case)
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M. Frank, EEL3705 Digital Logic, Spring 2007

32. Most Frequent Mistakes in Doing K-maps
Labeling rows/columns in wrong order
Don’t use the normal binary order 00,01,10,11 (wrong); use 00,01,11,10 (right)
Copying truth table column into the K-map rows & columns in the wrong order
It may help to first sequentially number all of the cells.
Drawing groupings of shapes other than rectangles, or that don’t contain a power of 2 cells (2,4,8,etc.), or that contain some 0s.
If group is not rectangular, 0’s are contained in it, or the number of cells is not equal a power of 2, then it does not correspond to any valid product term!
Drawing groupings that are not the largest possible!
If a group can be combined with a neighboring group, then it must be combined, in order to produce an equation with fewer (and smaller) product terms
Failing to consider groupings that go off the edges of the board
left-right and/or top/bottom edges
Failing to take full advantage of don’t-cares in one’s map
They are wildcards; use some as 1s if this helps increase the size of existing groupings
Failing to select an optimal cover
Often the EPIs will not cover all the 1s, and you may also have to select from among various different possible sets of the non-essential PIs. Some sets may be smaller than others! Choose the one with the fewest PIs (fewest product terms) in it.
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M. Frank, EEL3705 Digital Logic, Spring 2007

33. Tips on Schematic Entry with Subcircuits
Create each important subcircuit in its own individual .bdf file (block diagram file).
Make sure you include all of its I/O ports.
Select menu item “File -> Create/Update -> Create Symbol Files for Current File.”
This creates the .bsf file (block symbol file)
This contains a drawing of a “block” icon for your circuit, with input/output ports.
Make sure the file is added to your project, and then in the top-level file for your project,
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34. M. Frank, EEL3705 Digital Logic, Spring 2007
Screenshot showing how we select the icon for our own custom logic block to insert
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35. M. Frank, EEL3705 Digital Logic, Spring 2007
Karnaugh Maps (K-Map)
A K-Map is a graphical representation of a logic function’s truth table from which one can quickly calculate the simplest sum-of-products (or product-of-sums) representation of the function
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36. Relationship to Venn Diagrams
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37. Relationship to Venn Diagrams
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38. Relationship to Venn Diagramsb
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39. Relationship to Venn Diagramsb
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40. Relationship to Venn Diagrams
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41. M. Frank, EEL3705 Digital Logic, Spring 2007
Two-Variable K-Map
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42. Three-Variable K-Map
Note: The bit sequences must always be ordered using a Gray code!
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43. Three-Variable K-Map
Note: The bit sequences must always be ordered using a Gray code!
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44. Three-Variable K-Map
Note: The bit sequences must always be ordered using a Gray code!
Edges are adjacent
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45. Four-variable K-Map
Note: The bit sequences must be ordered using a Gray code!
Note: The bit sequences must be ordered using a Gray code!
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46. M. Frank, EEL3705 Digital Logic, Spring 2007
Four-variable K-Map
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47. M. Frank, EEL3705 Digital Logic, Spring 2007
Four-variable K-Map
Edges are adjacent
Edges are adjacent
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48. Plotting Functions on the K-map
SOP Form
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49. Canonical SOP Form Three Variable Example using shorthand notation
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50. Three-Variable K-Map Example
Plot 1’s (minterms) of switching function 1 1 1 1
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51. Three-Variable K-Map Example
Plot 1’s (minterms) of switching function 1 1 1 1
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52. Four-variable K-Map Example1 1 1 1 1
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53. Simplification of Switching Functions using K-MAPS
Karnaugh Maps (K-Map)
Simplification of Switching Functions
using K-MAPS
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54. Terminology/Definition
Literal
A variable or its complement
Logically adjacent terms
Two minterms are logically adjacent if they differ in only one variable position
Ex:
and
m6 and m2 are logically adjacent
Note:
Or, logically adjacent terms can be combined
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55. Terminology/Definition
Implicant
Product term that could be used to cover minterms of a function
Prime Implicant
An implicant that is not part of another implicant
Essential Prime Implicant
A prime implicant that covers at least one minterm that is not contained in another prime implicant
Cover
A minterm that has been used in at least one group
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56. Guidelines for Simplifying Functions
Each square on a K-map of n variables has n logically adjacent squares. (i.e. differing in exactly one variable)
When combing squares, always group in powers of 2m , where m=0,1,2,….
In general, grouping 2m variables eliminates m variables.
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57. Guidelines for Simplifying Functions
Group as many squares as possible. This eliminates the most variables.
Make as few groups as possible. Each group represents a separate product term.
You must cover each minterm at least once. However, it may be covered more than once.
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M. Frank, EEL3705 Digital Logic, Spring 2007

58. K-map Simplification Procedure
Plot the K-map
Circle all prime implicants on the K-map
Identify and select all essential prime implicants for the cover.
Select a minimum subset of the remaining prime implicants to complete the cover.
Read the K-map
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59. M. Frank, EEL3705 Digital Logic, Spring 2007
Example
Use a K-Map to simplify the following Boolean expression
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60. Three-Variable K-Map Example
Step 1: Plot the K-map 1 1 1 1 1
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61. Three-Variable K-Map Example
Step 2: Circle ALL Prime Implicants 1 1 1 1 1
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62. Three-Variable K-Map Example
Step 3: Identify Essential Prime Implicants PI
EPI PI 1 1
EPI 1 1 1
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63. Three-Variable K-Map Example
Step 4: Select minimum subset of remaining
Prime Implicants to complete the cover. PI
EPI 1 1
EPI 1 1 1
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64. Three-Variable K-Map Example
Step 5: Read the map. 1 1 1 1 1
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65. M. Frank, EEL3705 Digital Logic, Spring 2007
Solution
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66. M. Frank, EEL3705 Digital Logic, Spring 2007
Example
Use a K-Map to simplify the following Boolean expression
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67. Three-Variable K-Map Example
Step 1: Plot the K-map 1 1 1 1
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68. Three-Variable K-Map Example
Step 2: Circle Prime Implicants
Wrong!!
We really
should draw
A circle around
all four 1’s 1 1 1 1
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69. Three-Variable K-Map Example
Step 3: Identify Essential Prime Implicants
EPI
EPI
Wrong!!
We really
should draw
A circle around
all four 1’s 1 1 1 1
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70. Three-Variable K-Map Example
Step 4: Select Remaining Prime Implicants to
complete the cover.
EPI
EPI 1 1 1 1
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71. Three-Variable K-Map Example
Step 5: Read the map. 1 1 1 1
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72. M. Frank, EEL3705 Digital Logic, Spring 2007
Solution
Since we can still simplify the function
this means we did not use the largest
possible groupings.
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73. Three-Variable K-Map Example
Step 2: Circle Prime Implicants
Right! 1 1 1 1
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74. Three-Variable K-Map Example
Step 3: Identify Essential Prime Implicants
EPI 1 1 1 1
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75. Three-Variable K-Map Example
Step 5: Read the map. 1 1 1 1
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76. M. Frank, EEL3705 Digital Logic, Spring 2007
Solution
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77. M. Frank, EEL3705 Digital Logic, Spring 2007
Special Cases
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78. Three-Variable K-Map Example1 1 1 1 1 1 1 1
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79. Three-Variable K-Map Example
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80. Three-Variable K-Map Example1 1 1 1
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81. Four Variable Examples
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82. M. Frank, EEL3705 Digital Logic, Spring 2007
Example
Use a K-Map to simplify the following Boolean expression
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83. M. Frank, EEL3705 Digital Logic, Spring 2007
Four-variable K-Map 1 1 1 1 1 1 1 1
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84. M. Frank, EEL3705 Digital Logic, Spring 2007
Four-variable K-Map 1 1 1 1 1 1 1 1
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85. M. Frank, EEL3705 Digital Logic, Spring 2007
Four-variable K-Map 1 1 1 1 1 1 1 1
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86. M. Frank, EEL3705 Digital Logic, Spring 2007
Example
Use a K-Map to simplify the following Boolean expression
D=Don’t care (i.e. either 1 or 0)
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87. M. Frank, EEL3705 Digital Logic, Spring 2007
Four-variable K-Map 1 d 1 1 1 d 1 d 1 1
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88. M. Frank, EEL3705 Digital Logic, Spring 2007
Four-variable K-Map 1 d 1 1 1 d 1 d 1 1
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89. M. Frank, EEL3705 Digital Logic, Spring 2007
Five Variable K-Maps
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90. M. Frank, EEL3705 Digital Logic, Spring 2007
Five variable K-map
Use two four variable K-maps
A=1
A=0
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91. Use Two Four-variable K-Maps
A=0 map
A=1 map
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92. M. Frank, EEL3705 Digital Logic, Spring 2007
Five variable example
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93. Use Two Four-variable K-Maps
A=0 map
A=1 map 1 1 1 1 1 1 1 1
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94. Use Two Four-variable K-Maps
A=0 map
A=1 map 1 1 1 1 1 1 1 1
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95. M. Frank, EEL3705 Digital Logic, Spring 2007
Five variable example
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96. Plotting POS Functions
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97. K-map Simplification Procedure
Plot the K-map for the function F
Circle all prime implicants on the K-map
Identify and select all essential prime implicants for the cover.
Select a minimum subset of the remaining prime implicants to complete the cover.
Read the K-map
Use DeMorgan’s theorem to convert F to F in POS form
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98. M. Frank, EEL3705 Digital Logic, Spring 2007
Example
Use a K-Map to simplify the following Boolean expression
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99. Three-Variable K-Map Example
Step 1: Plot the K-map of F 1 1 1 1 1
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100. Three-Variable K-Map Example
Step 2: Circle ALL Prime Implicants 1 1 1 1 1
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101. Three-Variable K-Map Example
Step 3: Identify Essential Prime Implicants PI
EPI PI 1 1
EPI 1 1 1
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102. Three-Variable K-Map Example
Step 4: Select minimum subset of remaining
Prime Implicants to complete the cover. PI
EPI 1 1
EPI 1 1 1
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103. Three-Variable K-Map Example
Step 5: Read the map. 1 1 1 1 1
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104. M. Frank, EEL3705 Digital Logic, Spring 2007
Solution
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