1. Malik Najmus Siraj siraj@case.edu.pk
Digital Logic Design
Malik Najmus Siraj

2. Digital Logic Design@CASE by Najmus Siraj
Today’s Agenda
Recap
State machine task
Registers
JK flip flop and T flip Flop
Counter with state machine
Counters
State machine with JK and T flip flop
One hot encoding
Digital Logic by Najmus Siraj

3. Characteristic table and Equation
Digital Logic by Najmus Siraj

4. Digital Logic Design@CASE by Najmus Siraj
Design a circuit that meets the following specifications:
The circuit has one input, w, and one output, z.
All changes in the circuit occur on the positive edge of the clock signal.
Output z=1 if the input was 1 during the two immediately preceding clock cycles.
You are required to Design the following things
State machine
State Table
Minimized circuit diagram (Use K-map to minimize equations).
State machine task
Digital Logic by Najmus Siraj

5. Digital Logic Design@CASE by Najmus Siraj

6. State machine using JK flip flop
Digital Logic by Najmus Siraj

7. Digital Logic Design@CASE by Najmus Siraj
One hot encoding
Digital Logic by Najmus Siraj

8. Digital Logic Design@CASE by Najmus Siraj
JK flip flop example
Digital Logic by Najmus Siraj

9. Digital Logic Design@CASE by Najmus Siraj
Counters
Digital Logic by Najmus Siraj

10. Digital Logic Design@CASE by Najmus Siraj
Ripple counter
Digital Logic by Najmus Siraj

11. Digital Logic Design@CASE by Najmus Siraj
Ripple counter
Digital Logic by Najmus Siraj

12. Digital Logic Design@CASE by Najmus Siraj
Synchronous counter
Digital Logic by Najmus Siraj

13. Digital Logic Design@CASE by Najmus Siraj

14. Digital Logic Design@CASE by Najmus Siraj
Up down counter
Digital Logic by Najmus Siraj

15. Digital Logic Design@CASE by Najmus Siraj
Ring counter
Digital Logic by Najmus Siraj

16. Digital Logic Design@CASE by Najmus Siraj

17. Digital Logic Design@CASE by Najmus Siraj
State Reduction
Digital Logic by Najmus Siraj

18. Digital Logic Design@CASE by Najmus Siraj

19. Digital Logic Design@CASE by Najmus Siraj

20. Digital Logic Design@CASE by Najmus Siraj

21. Digital Logic Design@CASE by Najmus Siraj

22. Digital Logic Design@CASE by Najmus Siraj

23. Digital Logic Design@CASE by Najmus Siraj

24. Digital Logic Design@CASE by Najmus Siraj
Serial data transfer
Digital Logic by Najmus Siraj

25. Digital Logic Design@CASE by Najmus Siraj
Shift register
Digital Logic by Najmus Siraj

26. Serial transfer example
Digital Logic by Najmus Siraj

27. Digital Logic Design@CASE by Najmus Siraj
Serial addition
Digital Logic by Najmus Siraj

29. Maximum Register to Register delay
G10 TCQ + G7 Tpd + G6 Tpd + G8 Tpd + G10 Tsu = = 17ns
Maximum clock to out delay
G5 Tpd + G10 TCQ + G7 Tpd + G6 Tpd + G8 Tpd + G11 Tpd + G13 Tpd =
= = 29 ns
Maximum pin to pin delay (that is not clock to out delay)
G4 Tpd + G7 Tpd + G6 Tpd + G8 Tpd + G11 Tpd + G13 Tpd
= = 26 ns
Setup time on B input
G2 Tpd + G6 Tpd +G8 Tpd + G10 Tsu – G5 Tpd = – 5 = 10ns