Principles of Computers 21st Lecture

Principles of Computers 21st Lecture
Pavel Ježek, Ph.D.

Thread T1 Inserting into A Doubly-Linked List
T1: NewItem^.prev := AfterThis; T1: AfterThis^.next^.prev := NewItem; T1: NewItem^.next := AfterThis^.next; T1: AfterThis.next := NewItem; next prev NewItem next prev AfterThis next prev BeforeThis

Threads T1 and T2 Inserting into A Doubly-Linked List
T1: NewItem^.prev := AfterThis; T1: AfterThis^.next^.prev := NewItem; T1: NewItem^.next := AfterThis^.next; T1: AfterThis.next := NewItem; next prev NewItem next prev AfterThis next prev BeforeThis

T1: NewItem^.prev := AfterThis; T1: AfterThis^.next^.prev := NewItem; T1: NewItem^.next := AfterThis^.next; T1: AfterThis.next := NewItem; Context Switch next prev NewItem next prev AfterThis next prev BeforeThis

T1: NewItem^.prev := AfterThis; T1: AfterThis^.next^.prev := NewItem; T2: OtherItem^.prev := AfterThis; T2: AfterThis^.next^.prev := OtherItem; T2: OtherItem^.next := AfterThis^.next; T2: AfterThis.next := OtherItem; T1: NewItem^.next := AfterThis^.next; T1: AfterThis.next := NewItem; Context Switch next prev NewItem next prev AfterThis next prev BeforeThis next prev OtherItem

T1: NewItem^.prev := AfterThis; T1: AfterThis^.next^.prev := NewItem; T2: OtherItem^.prev := AfterThis; T2: AfterThis^.next^.prev := OtherItem; T2: OtherItem^.next := AfterThis^.next; T2: AfterThis.next := OtherItem; T1: NewItem^.next := AfterThis^.next; T1: AfterThis.next := NewItem; next prev NewItem next prev AfterThis next prev BeforeThis next prev OtherItem

T1: NewItem^.prev := AfterThis; T1: AfterThis^.next^.prev := NewItem; T2: OtherItem^.prev := AfterThis; T2: AfterThis^.next^.prev := OtherItem; T2: OtherItem^.next := AfterThis^.next; T2: AfterThis.next := OtherItem; T1: NewItem^.next := AfterThis^.next; T1: AfterThis.next := NewItem; Context Switch next prev NewItem next prev AfterThis next prev BeforeThis next prev OtherItem Still a valid doubly-linked list

T1: NewItem^.prev := AfterThis; T1: AfterThis^.next^.prev := NewItem; T2: OtherItem^.prev := AfterThis; T2: AfterThis^.next^.prev := OtherItem; T2: OtherItem^.next := AfterThis^.next; T2: AfterThis.next := OtherItem; T1: NewItem^.next := AfterThis^.next; T1: AfterThis.next := NewItem; next prev NewItem next prev AfterThis next prev BeforeThis next prev OtherItem

Is It Thread Safe? procedure InsertItem(AfterThis : Node; NewItem : Node) begin NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; end; next prev NewItem next prev AfterThis next prev BeforeThis

Is It Thread Safe? In Cooperative Multitasking?
procedure InsertItem(AfterThis : Node; NewItem : Node) begin Yield; { allowed here } NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; no Yield here! NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; end; next prev NewItem next prev AfterThis next prev BeforeThis

Is It Thread Safe? In Preemptive Multitasking?
procedure InsertItem(AfterThis : Node; NewItem : Node) begin NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; end; next prev NewItem next prev AfterThis next prev BeforeThis

procedure InsertItem(AfterThis : Node; NewItem : Node) begin NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; end; Critical Section next prev NewItem next prev AfterThis next prev BeforeThis

procedure InsertItem(AfterThis : Node; NewItem : Node) begin asm CLI; NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; asm STI; end; next prev NewItem next prev AfterThis next prev BeforeThis

procedure InsertItem(AfterThis : Node; NewItem : Node) begin asm CLI; NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; asm STI; end; PROBLEM: CLI is a privileged instruction → not available to normal applications (only kernel code can use it). If apps were allowed to use CLI, then kernel would not be able to preempt them from a [disabled] timer interrupt! next prev NewItem next prev AfterThis next prev BeforeThis

procedure InsertItem(AfterThis : Node; NewItem : Node) begin NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; end; Critical Section next prev NewItem next prev AfterThis next prev BeforeThis

procedure InsertItem(AfterThis : Node; NewItem : Node) begin NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; end; Critical Section next prev NewItem next prev AfterThis next prev BeforeThis Protection by means of mutual exclusion

Is It Thread Safe? Using Locks?
procedure InsertItem(AfterThis : Node; NewItem : Node) begin Lock(l); NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; Unlock(l); end; next prev NewItem next prev AfterThis next prev BeforeThis Protection by means of mutual exclusion - LOCKs

Possible Lock/Unlock Implementation on Uniprocessor System in Kernel
procedure InsertItem(AfterThis : Node; NewItem : Node) begin SysCall Lock(l) ... in kernel mode: asm CLI; while l.LockOwner <> nil do begin WaitForLock(l); threads[currTID].State := WAITING; threads[currTID].WakeupCondition := LOCK(l); Yield; end; l.LockOwner := currentThread; asm STI; NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; SysCall Unlock(l) ... in kernel mode: l.LockOwner := nil; WakeupThreadsWaitingOnLock(l);

Possible Lock/Unlock Implementation on Uniprocessor System in Kernel: CLI/STI Is Necessary
procedure InsertItem(AfterThis : Node; NewItem : Node) begin SysCall Lock(l) ... in kernel mode: asm CLI; while l.LockOwner <> nil do begin WaitForLock(l); threads[currTID].State := WAITING; threads[currTID].WakeupCondition := LOCK(l); Yield; end; l.LockOwner := currentThread; asm STI; NewItem^.prev := AfterThis; AfterThis^.next^.prev := NewItem; NewItem^.next := AfterThis^.next; AfterThis.next := NewItem; SysCall Unlock(l) ... in kernel mode: l.LockOwner := nil; WakeupThreadsWaitingOnLock(l); Without CLI/STI: RACE CONDITION: A: Owner=nil CTXSWITCH B: Owner=nil, B: Owner:=B CTXSWITCH A: Owner:=A

Lock Granularity

Locking Multiple Locks

System Bus

Atari Example in Pascal

Sending 1 Byte Via Philips PCA9564 I2C HBA
W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) R I2CCON → wait for SI=1 (controller waits for I2C idle state) R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) R I2CCON → wait for SI=1 R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send R I2CSTA → $28=ACK received → $30=NACK received W I2CCON ← (STA=0,STO=1) Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O)

Sending 1 Byte Via Philips PCA9564 I2C HBA
W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) R I2CCON → wait for SI=1 (controller waits for I2C idle state) R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) R I2CCON → wait for SI=1 R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send R I2CSTA → $28=ACK received → $30=NACK received W I2CCON ← (STA=0,STO=1) Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) If everything is ideal: 1 transaction on I2C bus = 11 transactions on system bus (or more, if not ideal)

Sending 1 Byte Using Interrupts
procedure SendByte(…); begin W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) set interrupt X handler end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send set interrupt X handler procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received W I2CCON ← (STA=0,STO=1) set interrupt X handler = default Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O)

procedure SendByte(…); begin W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) set interrupt X handler end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send set interrupt X handler procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received W I2CCON ← (STA=0,STO=1) set interrupt X handler = default Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) RACE CONDITION!

procedure SendByte(…); begin W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) set interrupt X handler end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send set interrupt X handler procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received W I2CCON ← (STA=0,STO=1) set interrupt X handler = default Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) RACE CONDITION! If controller is fast and interrupt arrives here, we will send the same data byte for the second time!

procedure SendByte(…); begin W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) set interrupt X handler end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost W I2CDAT ← data byte to send set interrupt X handler procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received W I2CCON ← (STA=0,STO=1) set interrupt X handler = default Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) RACE CONDITION! Preemptive multitasking: if interrupts enabled, timer interrupt can also arrive here, and Yield us! So even for slow controller, controller’s interrupt can arrive here, and we will send the same data byte for the second time! If interrupt arrives here, we will send the same data byte for the second time!

procedure SendByte(…); begin W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) set interrupt X handler end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) W I2CDAT ← (slave addr|R/W=0=write) set interrupt X handler procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost STI W I2CDAT ← data byte to send set interrupt X handler procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received W I2CCON ← (STA=0,STO=1) set interrupt X handler = default Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) RACE CONDITION! Solution 1: Do NOT re-enable interrupts too soon!

procedure SendByte(…); begin set interrupt X handler W I2CCON ← (STA=1|STO=0|CR0-CR2=clock rate) end; procedure SendAddress(…); begin R I2CSTA → $08=start transmitted W I2CCON ← (STA=0,STO=0) set interrupt X handler W I2CDAT ← (slave addr|R/W=0=write) procedure SendData(…); begin R I2CSTA → $18=ACK received=slave listening → $20=NACK received=slave not present → $38=arbitration lost set interrupt X handler W I2CDAT ← data byte to send procedure SendStop(…); begin R I2CSTA → $28=ACK received → $30=NACK received set interrupt X handler = default W I2CCON ← (STA=0,STO=1) Registers I2CCON = Control (R/W) bit STA: 1 = send Start condition bit STO: 1 = send Stop condition bit SI = Serial Interrupt: 1 = Status register changed (SCL line is held LOW → I2C transmission is suspended) I2CDAT = Data (R/W) I2CSTA = Status (R/O) Solution 2: Reverse order of installing new interrupt handler and starting new command execution in the controller!

Graphics Card HCI

8-bit Sound Card HCI DAC Address decode Playback logic Data W/O reg
sound buffer (100kB – MB) RWAddr reg ... $F $F DD $F $F $F $F DAC PlayAdr reg auto increment auto increment Loudspeaker image (CC Attribution) authored by Sallee Design,

16-bit Sound Card HCI (Byte Ordering as Part of HCI)
Address decode Playback logic Data W/O reg MSB LSB sound buffer (100kB – MB) RWAddr reg ... $F DD $F $F $F $F $F DAC PlayAdr reg auto increment on MSB write (LSB and MSB must be written at once during a single 16-bit write [if on 16-bit system bus] or LSB must be written first and MSB second if on 8-bit system bus) auto increment Loudspeaker image (CC Attribution) authored by Sallee Design,

MSB LSB sound buffer (100kB – MB) RWAddr R/W reg ... $F DD $F $F AA $F $F $F DAC PlayAdr reg auto increment auto increment Loudspeaker image (CC Attribution) authored by Sallee Design,

MSB LSB sound buffer (100kB – MB) RWAddr R/W reg ... $F DD $F $F AA $F CF $F $F DAC PlayAdr reg auto increment Config R/W reg ▪sample rate ▪sample size ▪mono/stereo auto increment Loudspeaker image (CC Attribution) authored by Sallee Design,

16-bit Sound Card HCI DAC Address decode Playback logic Data R/W reg
MSB LSB sound buffer (100kB – MB) RWAddr R/W reg ... $F DD $F $F AA $F CF $F CT $F DAC PlayAdr reg auto increment Config R/W reg ▪sample rate ▪sample size ▪mono/stereo auto increment Control W/O reg ▪play/stop ▪record/stop Loudspeaker image (CC Attribution) authored by Sallee Design,

MSB LSB sound buffer (100kB – MB) RWAddr R/W reg ... $F DD $F $F AA $F CF $F CT $F ST DAC PlayAdr reg auto increment Config R/W reg ▪sample rate ▪sample size ▪mono/stereo auto increment Control W/O reg ▪play/stop ▪record/stop Status R/O reg ▪play position ▪playing? ▪recording? Loudspeaker image (CC Attribution) authored by Sallee Design, Base address: $F

PIO (Programmed I/O) – Reading 1 Byte From Controller
6502: LDA ctrl_data_reg_address STA buffer_address

PIO (Programmed I/O) 6502: 1 tx = read/fetch load instruction opcode
LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx

LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx 6502: LDA addr = 3 byte instruction STA addr = 3 byte instruction 3 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 3 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 8 tx

LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx 6502: LDA addr = 3 byte instruction STA addr = 3 byte instruction 3 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 3 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 8 tx e.g. system bus: 1 byte/tx 2 cycles/tx 1 MHZ cycles = 0,5 MB/second = x B/s PIO transfer = (x / 8) B/s = 62,5 kB/s

PIO (Programmed I/O) Solution: DMA 6502:
LDA ctrl_data_reg_address STA buffer_address 1 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 1 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 4 tx 6502: LDA addr = 3 byte instruction STA addr = 3 byte instruction 3 tx = read/fetch load instruction opcode 1 tx = read data from controller’s data register 3 tx = read/fetch store instruction opcode 1 tx = write data from A to buffer in memory = 8 tx e.g. system bus: 1 byte/tx 2 cycles/tx 1 MHZ cycles = 0,5 MB/second = x B/s PIO transfer = (x / 8) B/s = 62,5 kB/s Solution: DMA

MSB LSB sound buffer (100kB – MB) RWAddr R/W reg ... $F DD $F $F AA $F CF $F CT $F ST DAC PlayAdr reg auto increment Config R/W reg ▪sample rate ▪sample size ▪mono/stereo auto increment Control W/O reg ▪play/stop ▪record/stop Status R/O reg ▪play position ▪playing? ▪recording? Loudspeaker image (CC Attribution) authored by Sallee Design, Base address: $F

16-bit Sound Card HCI with DMA Bus Master
Address decode Playback logic DMA Addr R/W reg 32-bit ... $F000010A A3 $F A2 $F A1 $F A0 $F L3 $F L2 $F L1 $F L0 $F CF $F CT $F ST sound buffer (100kB – MB) auto increment DMA Length R/W reg 32-bit DAC PlayAdr reg DMA BufferAddr reg Config R/W reg ▪sample rate ▪sample size ▪mono/stereo auto increment auto increment Control W/O reg ▪play/stop ▪record/stop Status R/O reg ▪play position ▪playing? ▪recording? Loudspeaker image (CC Attribution) authored by Sallee Design, Base address: $F

DMA: Do Not Forget: Logical vs. Physical Address Space
CPU arch. CPU name Data width Logical address width Current instruction register(s) Physical address width 8-bit 6502 MOS 6502 8-bit data 16-bit PC (64 kB) x86-16 x86 Intel 8088 bit 20-bit (1 MB) Intel 8086 16-bit data logical address (16 bit & 16 bit): Segment:Offset physical address (20 bit): (Segment * 16) + Offset logical address: $AAAA:$0000 physical address: $AAAA * 16 = $AAAA shl 4 = $AAAA0 + $0000 = $AAAA0

kernel fdfd system bus RS-232 controller driver Serial API RS-232
RS-232 controller HCI: $3F8-$3FF IRQ 4 Serial API RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 Serial API I2C controller driver I2C controller HCI (registers, IRQ) Operating system API I2C API IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA Disk API VGA graphics card driver VGA HCI: $000A000-$000AFFF Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Keyb API

kernel fdfd HAL system bus RS-232 controller driver Serial API RS-232
RS-232 controller HCI: $3F8-$3FF IRQ 4 Serial API RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 Serial API I2C controller driver I2C controller HCI (registers, IRQ) Operating system API I2C API IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA Disk API VGA graphics card driver VGA HCI: $000A000-$000AFFF Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Keyb API

kernel fdfd HAL system bus serial mouse driver RS-232 controller
RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 ALS API I2C API Serial API I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA Disk API VGA graphics card driver VGA HCI: $000A000-$000AFFF Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Keyb API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver ReadSector(sectorNumber : longword; buffer : ^byte); WriteSector(sectorNumber : longword; buffer : ^byte); RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 ALS API I2C API Serial API I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA FileSys API Disk API Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver ReadSector(sectorNumber : longword; buffer : ^byte); WriteSector(sectorNumber : longword; buffer : ^byte); RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Win32 API: equivalent function is named CreateFile – as an abbreviation from CreateNewFileDescriptorHandle Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Win32 API: FD is called handle Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

kernel fdfd HAL Process state (context): system bus
Allocated memory (pages) CPU fault → kernel interrupt handler call procTable[currentPID].faultHandlers[faultID] List of loaded DLLs Page table (state of the address space) PID (Process ID) Open files – e.g. ReadFile(fileDesc, ...): read from procTable[currentPID].fileDescTable[fileDesc] HAL serial mouse driver RS-232 controller driver RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

Doing Something Usefull (Other Threads Run) When Waiting for IRQ
procedure syscall_ReadFile(fileDesc : longword, ...); begin completed := procTable[currentPID].fdt[fileDesc]^.driver.readProcPtr(...); if not(completed) then begin threadTable[currTID].State := WAITING; threadTable[currTID].WakeupCondition := WakeupOnFileDescritor(fileDesc); Yield; end; IRQ: driver_InterruptHandler: communicate with the controller are further requests necessary? YES: command the controller to execute next request NO: WakeupAllThreads(WakeupOnFileDescritor(currRequest^.fileDesc) IRET

kernel fdfd HAL Process state (context): system bus
Allocated memory (pages) CPU fault → kernel interrupt handler call procTable[currentPID].faultHandlers[faultID] List of loaded DLLs Page table (state of the address space) PID (Process ID) Open files – e.g. ReadFile(fileDesc, ...): read from procTable[currentPID].fileDescTable[fileDesc] Current path – e.g. OpenFile(path, ...) if path startsWith ‘/’ or ‘\’ then open file at (path) else open file at (procTable[currentPID].workingDir + path) HAL serial mouse driver RS-232 controller driver RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) ext3 filesystem driver FileSys API NTFS filesystem driver IDE disk controller driver IDE HDC HCI: $170-$177,$376 IRQ 15,DMA FileSys API Disk API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API VFS: C: D: E: I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) ext3 filesystem driver FileSys API NTFS filesystem driver IDE disk controller driver IDE HDC HCI: $170-$177,$376 IRQ 15,DMA FileSys API Disk API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API VFS: C: I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API VFS: MOUSE ALS1 ALS2 C: CON I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API VFS: MOUSE ALS1 ALS2 C: CON I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Ioctl(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

kernel fdfd HAL system bus RS-232 controller driver Serial API RS-232
RS-232 controller HCI: $3F8-$3FF IRQ 4 Serial API RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) Serial API VFS: COM1 COM3 ALS2 C: CON I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Ioctl(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API

Communication Over RS-232 Example From 2nd Lecture
... comPortName := 'COM3'; serialHandle := SerOpen(comPortName); repeat bytesRead := SerReadTimeout(serialHandle, byte1, 100); if bytesRead = 1 then begin SerReadTimeout(serialHandle, byte2, 100); SerReadTimeout(serialHandle, byte3, 100); SerReadTimeout(serialHandle, byte4, 100); Write('Packet[', byte1, ' ', byte2, ' ', byte3, ' ', byte4, '] '); end; until KeyPressed;

Communication Over RS-232 Example From 2nd Lecture
... comPortName := 'COM3'; serialHandle := SerOpen(comPortName); repeat bytesRead := SerReadTimeout(serialHandle, byte1, 100); if bytesRead = 1 then begin SerReadTimeout(serialHandle, byte2, 100); SerReadTimeout(serialHandle, byte3, 100); SerReadTimeout(serialHandle, byte4, 100); Write('Packet[', byte1, ' ', byte2, ' ', byte3, ' ', byte4, '] '); end; until KeyPressed; Serial.pp: function SerOpen(const DeviceName: String): TSerialHandle; begin ... result := CreateFile( PChar(DeviceName), GENERIC_READ or GENERIC_WRITE, 0, @securityAttributes, OPEN_EXISTING, 0); if result = INVALID_HANDLE_VALUE then result := 0 else end; function SerRead(Handle: TSerialHandle; var Buffer; Count: LongInt): LongInt; var BytesRead: DWORD; Timeouts: TCommTimeouts; if not ReadFile(Handle, Buffer, Count, BytesRead, nil) then result := BytesRead

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API word GetStdFd(STDIN or STDOUT) I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API VFS: MOUSE ALS1 ALS2 C: CON I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Ioctl(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API A’s file descriptor table (FDT) STDIN FD STDOUT FD Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API VFS view by process A

RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API word GetStdFd(STDIN or STDOUT) Pascal RTL: procedure Write(i : integer); var fd : word; s : string; begin Str(i, s); { standard Pascal procedure to convert integer to string } fd := GetStdFd(STDOUT); Length(s)); end; I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API VFS: MOUSE ALS1 ALS2 C: CON I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Ioctl(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API A’s file descriptor table (FDT) STDIN FD STDOUT FD Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API VFS view by process A

VFS view by another process B
fdfd system bus kernel HAL serial mouse driver RS-232 controller driver RS-232 controller HCI: $3F8-$3FF IRQ 4 Mouse API Serial API word GetStdFd(STDIN or STDOUT) I2C ALS driver RS-232 to I2C bridge driver RS-232 controller driver RS-232 controller HCI: $2F8-$2FF IRQ 3 word OpenFile(name : string) ALS API I2C API Serial API VFS: MOUSE ALS1 ALS2 C: CON I2C ALS driver I2C controller driver I2C controller HCI (registers, IRQ) Operating system API ALS API I2C API FAT filesystem driver IDE disk controller driver IDE HDC HCI: $1F0-$1F7,$3F6 IRQ 14,DMA ReadFile(fd : word; ...) FileSys API Disk API WriteFile(fd : word; ...) Ioctl(fd : word; ...) Console window driver VGA graphics card driver VGA HCI: $000A000-$000AFFF Console API Graphics API B’s file descriptor table (FDT) STDIN FD STDOUT FD Keyboard controller driver keyboard controller HCI: $60-$64 IRQ 1 Console window driver Keyb API Console API VFS view by another process B

wasted physical memory
... kernel data IVT proc table A’s PT kernel code A stack guard page free 9 8 A data 7 A data (guard) 6 5 A code (guard) 4 3 A code 2 1 page 0 wasted physical memory How to use the otherwise wasted physical memory for another process, if this process A will never access these pages? A’s entrypoint page fault wasted physical memory Non-present Kernel/Supervisor User Read/Only User Read/Write wasted physical memory wasted physical memory

virtual address space (VA)
logical address: [e.g. for 1 kB = 210 B pages & 32-bit address space] logical address $000021F5 = 0000|0000|0000|0000|0010|0001|1111|0101 page number 0000|0000|0000|0000|0010|00 = $00008 offset 01|1111|0101 = $1F5 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 virtual address space (VA)

page number offset frame number offset
IVT proc table ... A’s PT kernel code A stack nothing free 11 10 0F 0E 0D 0C 0B 0A 09 A data 08 07 06 05 04 A code 03 02 01 00 logical address = virtual address if paging enabled: [e.g. for 1 kB = 210 B pages & 32-bit address space] virtual address $000021F5 = 0000|0000|0000|0000|0010|0001|1111|0101 page number 0000|0000|0000|0000|0010|00 = $00008 offset 01|1111|0101 = $1F5 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address: [e.g. for 1 kB = 210 B pages & 32-bit address space] frame number $00008 = 0000|0000|0000|0000|0010|00 offset $1F5 = 01|1111|0101 0000|0000|0000|0000|0010|0001|1111|0101 = $000021F5 physical address physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code A stack nothing free 11 10 0F 0E 0D 0C 0B 0A 09 A data 08 07 06 05 04 A code 03 02 01 00 logical address = virtual address if paging enabled: [e.g. for 1 kB = 210 B pages & 32-bit address space] virtual address $000021F5 = 0000|0000|0000|0000|0010|0001|1111|0101 page number 0000|0000|0000|0000|0010|00 = $00008 offset 01|1111|0101 = $1F5 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 PT entry: Frame = $00008 Access = 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address: [e.g. for 1 kB = 210 B pages & 32-bit address space] frame number $00008 = 0000|0000|0000|0000|0010|00 offset $1F5 = 01|1111|0101 0000|0000|0000|0000|0010|0001|1111|0101 = $000021F5 physical address physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code A stack nothing free 11 10 0F 0E 0D 0C 0B 0A 09 A data 08 07 06 05 04 A code 03 02 01 00 logical address = virtual address if paging enabled: [e.g. for 1 kB = 210 B pages & 32-bit address space] virtual address $000021F5 = 0000|0000|0000|0000|0010|0001|1111|0101 page number 0000|0000|0000|0000|0010|00 = $00008 offset 01|1111|0101 = $1F5 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 PT entry: Frame = $0000F Access = 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address: [e.g. for 1 kB = 210 B pages & 32-bit address space] frame number $0000F = 0000|0000|0000|0000|0011|11 offset $1F5 = 01|1111|0101 0000|0000|0000|0000|0011|1101|1111|0101 = $00003DF5 physical address physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code A stack nothing free 11 10 A data 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 A code 03 02 01 00 logical address = virtual address if paging enabled: [e.g. for 1 kB = 210 B pages & 32-bit address space] virtual address $000021F5 = 0000|0000|0000|0000|0010|0001|1111|0101 page number 0000|0000|0000|0000|0010|00 = $00008 offset 01|1111|0101 = $1F5 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 PT entry: Frame = $0000F Access = 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address: [e.g. for 1 kB = 210 B pages & 32-bit address space] frame number $0000F = 0000|0000|0000|0000|0011|11 offset $1F5 = 01|1111|0101 0000|0000|0000|0000|0011|1101|1111|0101 = $00003DF5 physical address physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code A stack nothing free 11 10 0F 0E 0D 0C 0B 0A 09 A data 08 07 06 05 04 A code 03 02 01 00 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 A code 00 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 A stack 01 A code 00 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 A code 02 A stack 01 00 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 A data 03 A code 02 A stack 01 00 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

IVT proc table ... A’s PT kernel code free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 A stack 04 A data 03 A code 02 01 00 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

FW ROM free MM I/O ... 11 10 0F 0E 0D 0C 0B 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs A’s PT kernel code A stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

FW ROM free MM I/O ... 11 10 0F 0E 0D 0C 0B A stack 0A 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address space (PA) virtual address space (VA)

free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 page 0 FW ROM MM I/O free VRAM ... 11 10 0F 0E 0D 0C 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 page 0 FW ROM MM I/O free VRAM ... 11 10 0F 0E 0D 0C 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A 09 ALLOC FOR HEAP 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C A heap 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A 09 A heap 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C A heap 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A ALLOC FOR HEAP 09 A heap 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C A heap 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B 0A A heap 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C A heap 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B ALLOC FOR HEAP 0A A heap 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C A heap 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B ALLOC FOR HEAP 0A A heap 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 B 06 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 B heap 0F B code 0E 0D B stack 0C A heap 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 TEMP FRAME $0F 0F 0E 0D 0C 0B ALLOC FOR HEAP 0A A heap 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 B 06 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 in swap: 00 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 A heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D 0C 0B A heap 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 B 06 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 in swap: 00 05 B data 04 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 A heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 A data 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D ALLOC FOR HEAP 2 0C ALLOC FOR HEAP 1 0B A heap 0A 09 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 A 08 02 B 04 01 B 06 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 in swap: 00 05 B data 04 in swap: 01 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 A heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D A heap 0C 0B 0A 09 08 in swap: 02 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

process B tries to access data on address in page 6 range
free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 A 08 02 B 04 01 B 06 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 in swap: 00 05 B data 04 in swap: 01 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 A heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D A heap 0C 0B 0A 09 08 in swap: 02 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 page file (swap) page fault B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 A 08 02 B 04 01 B 06 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 in swap: 00 05 B data 04 in swap: 01 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 A heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 08 A code 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D A heap 0C 0B 0A 09 08 in swap: 02 07 A data (guard) 06 05 A code (guard) 04 03 02 01 00 page 0 page file (swap) page fault B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 A 08 02 B 04 01 B 06 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code B stack guard page free ... 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 B heap 05 B data 04 in swap: 01 03 B code (guard) 02 B code 01 00 page 0 FW ROM MM I/O B data VRAM ... 11 10 A heap 0F B code 0E 0D B stack 0C 0B B’s PT 0A A stack 09 08 B heap 07 06 05 A’s PT 04 proc table 03 kernel code 02 01 IVT 00 kernel data IVT proc table ctrl regs B’s PT A’s PT kernel code A stack guard page ... free 11 10 0F 0E 0D A heap 0C 0B 0A 09 08 in swap: 02 07 A data (guard) 06 05 A code (guard) 04 03 02 01 00 page 0 Page 06 of process B was originally mapped to frame 0F, and now is mapped to frame 07. But this is fully transparent to the application! page file (swap) page fault B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

Bonus Slides Follow

DLL Code Sharing free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00
... kernel code B stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 Y.DLL data 08 07 Y.DLL code 06 X.DLL data 05 X.DLL code 04 03 B data 02 B code 01 00 page 0 ... free 11 A stack 10 X.DLL data 0F Z.DLL data 0E Z.DLL code 0D A data 0C A code 0B B stack 0A Y.DLL data 09 08 Y.DLL code 07 06 X.DLL code 05 04 B data 03 B code 02 01 kernel code 00 ... kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 X.DLL data 06 X.DLL code (guard) 05 X.DLL code 04 Z.DLL data 03 Z.DLL code 02 A data 01 A code 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

DLL Data Sharing via Copy on Write
free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 ... kernel code B stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 Y.DLL data 08 07 Y.DLL code 06 X.DLL data 05 X.DLL code 04 03 B data 02 B code 01 00 page 0 ... free 11 10 A stack 0F Z.DLL data 0E Z.DLL code 0D A data 0C A code 0B B stack 0A Y.DLL data 09 08 Y.DLL code 07 X.DLL data 06 X.DLL code 05 04 B data 03 B code 02 01 kernel code 00 ... kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 X.DLL data 06 X.DLL code (guard) 05 X.DLL code 04 Z.DLL data 03 Z.DLL code 02 A data 01 A code 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

DLL Data Sharing via Copy on Write
free 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 ... kernel code B stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 Y.DLL data 08 07 Y.DLL code 06 X.DLL data 05 X.DLL code 04 03 B data 02 B code 01 00 page 0 ... free 11 A X.DLL data 10 A stack 0F Z.DLL data 0E Z.DLL code 0D A data 0C A code 0B B stack 0A Y.DLL data 09 08 Y.DLL code 07 X.DLL data 06 X.DLL code 05 04 B data 03 B code 02 01 kernel code 00 ... kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 08 07 X.DLL data 06 X.DLL code (guard) 05 X.DLL code 04 Z.DLL data 03 Z.DLL code 02 A data 01 A code 00 page 0 page file (swap) B’s virtual address space (VA) physical address space (PA) A’s virtual address space (VA)

IVT proc table ... A’s PT kernel code A stack nothing free 11 10 A data 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 A code 03 02 01 00 logical address = virtual address if paging enabled: [e.g. for 1 kB = 210 B pages & 32-bit address space] virtual address $000021F5 = 0000|0000|0000|0000|0010|0001|1111|0101 page number 0000|0000|0000|0000|0010|00 = $00008 offset 01|1111|0101 = $1F5 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 PT entry: Frame = $0000F Access = 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 physical address: [e.g. for 1 kB = 210 B pages & 32-bit address space] frame number $0000F = 0000|0000|0000|0000|0011|11 offset $1F5 = 01|1111|0101 0000|0000|0000|0000|0011|1101|1111|0101 = $00003DF5 physical address physical address space (PA) virtual address space (VA)

(i7 in x64 mode: 64-bit VA, 48-bit PA)
Different sizes of virtual (e.g. 32 bit) and physical (e.g. 24 bit) address spaces are possible! (i7 in x64 mode: 64-bit VA, 48-bit PA) logical address = virtual address if paging enabled: [e.g. for 1 kB = 210 B pages & 32-bit address space] virtual address $000021F5 = 0000|0000|0000|0000|0010|0001|1111|0101 page number 0000|0000|0000|0000|0010|00 = $00008 offset 01|1111|0101 = $1F5 kernel data IVT proc table ... A’s PT kernel code A stack guard page free 11 10 0F 0E 0D 0C 0B 0A 09 PT entry: Frame = $00F Access = 08 A data 07 A data (guard) 06 05 A code (guard) 04 03 A code 02 01 00 page 0 IVT proc table ... A’s PT kernel code A stack A data 0F free 0E 0D 0C 0B 0A 09 08 nothing 07 06 05 04 A code 03 02 01 00 physical address: [e.g. for 1 kB = 210 B pages & 32-bit address space] frame number $00F = 0000|0000|0011|11 offset $1F5 = 01|1111|0101 0000|0000|0011|1101|1111|0101 = $003DF5 physical address physical address space (PA) virtual address space (VA)

Principles of Computers 21st Lecture

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Principles of Computers 21st Lecture

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