1. CH2 : Memory & IO map design

2. Micro computer system design memory map
address
function
0xFFFF
0x8000
SDRAM
memory
0x27FF
0x2700
Serial PORT
Serial communication port
0x26FF
0x2600
PORT_5(IN)
Input PORT
0x25FF
0x2500
PORT_4(OUT)
Out PORT
0x24FF
0x2400
PORT_3(IN)
0x23FF
0x2300
PORT_2(OUT)
0x22FF
0x2200
PORT_1(IN) : Key
8bit Key input
0x21FF
0x2100
PORT_0(OUT) : LED
8bit LED
0x20FF
0x2000
Text LCD
16x2 line text LCD

3. Micro computer system diagram
SRAM
0x8000
0xFFFF
CPU
address
0x2000
0x20FF
Text LCD
0x2100
0x21FF
PIO_0(OUT):LED
data
0x2200
0x22FF
PIO_1(IN)Key
control
0x2300
0x23FF
PIO_2(OUT)
0x2400
0x24FF
PIO_3(IN) ADC
Chip set
0x2500
0x25FF
PIO_4(OUT)
0x2600
0x26FF
PIO_5(IN)
0x2700
0x27FF
Address bus
Data bus
Control bus
Serial PORT

4. External SRAM 영역 I/O 영역 Internal 영역
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Use Memory
0xFFFF
External SRAM
0x8000
0x7FFF
0x4000
0x27FF
Serial PORT
0x2700
0x26FF
PIO_5(IN)
0x2600
0x25FF
Pio_4(OUT)
0x2500
0x24FF
Pio_3(input) ADC
0x2400
0x23FF
PIO_2(OUT)
0x2300
0x22FF
Key Input
0x2200
0x21FF
PIO_1 : LED
0x2100
0x20FF
Text LCD
0x2000
0x1FFF
NOT Use
0x1100
0x10FF
Internal SRAM(4096 byte)
0x0100
0x00FF
160 Exit I/O register(160 byte)
0x0060
0x005F
64 I/O register(64 byte)
0x0020
0x001F
Internal Register(3 2byte)
0x0000
External SRAM 영역
I/O 영역
Internal 영역

5. Micro computer system diagram
ATmega128 Demultiplexed Addressing method design
74HC573
LATCH
/INT0
PA0(AD0)
PA1(AD1)
PA2(AD2)
PA3(AD3)
PA4(AD4)
PA5(AD5)
PA6(AD6)
PA7(AD7)
PD0(INT0)
PD1(INT1)
PD2(INT2)
PD3(INT3)
PE0(RXD0)
PE1(TXD0)
/INT1
/INT2
A0~A7
/INT3
RXD0
TXD0
ALE
D0~D7
PC0(AD8)
PC1(AD9)
PC2(AD10)
PC3(AD11)
PC4(AD12)
PC5(AD13)
PC6(AD14)
PC7(AD15)
A8~A15
/WR
PG0(/WR)
PG1(/RD)
PG2(ALE))
/RD

6. ATmega128 CPU circuit

7. PLD PAL GAL 22V10-WinCUPL로 logic 구현 하기
Industry Standard Architecture
– Low Cost Easy-to-Use Software Tools
• High-Speed, Electrically-Erasable Pro
– 7.5 ns Maximum Pin-to-Pin Delay
• CMOS and TTL Compatible Inputs and Outputs
– Input and I/O Pull-Up Resistors
• High Reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles

10. Micro computer system diagram
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Use Memory
0xFFFF
External SRAM
0x8000
0x7FFF
0x4000
0x27FF
Pio_6(input)
0x2700
0x26FF
Pio_5(output)
0x2600
0x25FF
Pio_4(input)
0x2500
0x24FF
Pio_3(input)
0x2400
0x23FF
PIO_2(OUT)
0x2300
0x22FF
PIO_2 KEY_IN
0x2200
0x21FF
PIO_1 : LED
0x2100
0x20FF
Text LCD
0x2000

11. Micro computer system diagram
PLD를 이용한 system map design
Chip set
PLD PAL GAL 22V10
SRAM
AD15
/WR
PIN1(CLK)
PIN2(IN)
PIN3(IN)
PIN4(IN)
PIN5(IN)
PIN6(IN)
PIN7(IN)
PIN8(IN)
PIN9(IN)
PIN10(IN)
PIN11(IN)
PIN13(IN)
/RD
LCD_EN
Text LCD
A15
PIN14(OUT)
PIN15(OUT)
PIN16(OUT)
PIN17(OUT)
PIN18(OUT)
PIN19(OUT)
PIN20(OUT)
PIN21(OUT)
PIN22(OUT)
PIN23(OUT)
LCD_R/W
A14
LED
A13
KEY
PIO_1(OUT):LED
A12
A11
A10
Key A9 A8 A1
PIO_2(OUT) A0
PIO_3(IN)
PIO_4(OUT)
ADC
Address bus
Data bus
Control bus
Serial PORT

12. Micro computer system diagram
PIN 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22
213
function
/WR
/RD
A15
A14
A13
A12
A11
A10
A09
A08
A01
A00
LCD_E N
/LCD_R/W
LCD_RS
/LED _ CS
/KEY_/CS
P3OUT
P4IN_/CS
P5OUT_CS
P6IN_/CS
0x8000
0XFFFF *
SRAM
0x2600
PORT6 IN address
0x2500
PORT5 OUT address
0x2400
PORT4 IN address
0x2300
PORT3 OUT address
0x2200
KEY address
0x2100
LED address
0x2000
0x2001
0x2002
0x2003
LCD_IR_WR
LCD_IR)RD
LCD_DR_WR
LCD_DR_RD

14. Address bus, data bus, control bus design

15. SRAM interface
Power interface

16. LED interface
LCD interface

17. PORT3 interface
PORT4 interface
PORT5 interface
PORT6 interface

18. Key interface

19. Chip set interface SRAM /CS Serial communication port /CS PORT6(IN)
PORT5(OUT)
PORT4(IN)
PORT3(OUT)
Key PORT
LED PORT
LCD RS
LCD R/W
LCD EN

20. R-ARRAY POWER PORTG PORT5(OUT) 74HC573 62256 PORTA(add/data)
PORTC(address)
ATF22V10C
DATABUS
Address Bus
74HC573(P3)
74HC573(P5)
74HC541(P6)
74HC541(P4)
PORT6(IN)
SWITCH
PORT4(IN)
PORT3(OUT)
R-ARRAY
74HC541(key)
LED VR
HEADER(LCD)
RESISTOR & CAPACITOR
CHIPSET
RS R/W EN
74HC573(LED) CS
/CS
SW1 SW SW SW4
SW5 SW SW7 SW8
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PG2(ALE)
PG0(/WR)
PG1(/RD)
VCC
GND

23. ATmega128 memory map SRAM design
영역 : 0x8000~0xFFFF
Address
function
0xFFFF
0x8000
SRAM 영역
0x0000

24. SRAM 62256 KM62256C CMOS SRAM FEATURES PIN DESCRIPTION
· Process Technology : 0.7mm CMOS
· Organization : 32Kx8
· Power Supply Voltage : Single 5V±10%
· Low Data Retention Voltage : 2V(Min)
· Three state output and TTL Compatible · Package Type : 28-DIP-600, 28-SOP-450,
28-TSOP F/R
PIN DESCRIPTION

25. 74HC/HCT573 Octal D-type transparent latch; 3-state
Output device LATCH
74HC/HCT573 Octal D-type transparent latch; 3-state
74LS573을 사용할 경우
Output device chip select는 /CE=“L”, LE=“H”일 때
Data가 latch 된다.
따라서 CH신호를 “High”일때 active가 된다.

26. 74LS541,74HC245; 74HCT245 Octal bus tranceiver; 3-state
Input device Buffer
74LS541,74HC245; 74HCT245 Octal bus tranceiver; 3-state
74LS245을 사용할 경우
Input device chip select는 /CE=“L”, DIR=“L”일 때
Data가 A에서 B로 전송 된다.
따라서 CH신호를 “Low”일때 active가 된다.