1. Development of new CN for PXD DAQ
Zhen-An LIU
IHEP Beijing
25 Sep. 2010

2. Basic Functions of Generic CN

3. Architecture and features of GPDP
High Performance Compute Power/resources:
5 Virtex-4 FX60 FPGA
10Gb DDR2 RAM (2G/FPGA)
~32Gbps Bandwidth
8x panel Optical Link(3Gbps each)
13x RocketIO to backplane
5x Gigabit Ethernet
1x GBit Ethernet to backplane
2 Embedded PowerPC in each FPGA for slow control
Real time Linux
ATCA compliant

4. First Prototype FPGA #1-4 FPGA #O Optical Backplane Ethernet
DDR2 sockets

5. 2nd version prototype SFP pluggable Mono RJ45 socket
Higher bandwidth /SFP+
Front Pannel
Better LEDs

6. Requirement from PXD DDR memory 4G/FPGA(20G/CN) 6 Gbps/FPGA
A lot discussions which is still under going.

7. Guidelines for New version at IHEP
Which Platform
ATCA or XTCA
ATCA or ATCA Carrier + AMC
3.125Gbps/ch or 6.25Gbps/ch
DDR2 or DDR3 or DDR4, or ……
V4 or V5 or V6 or SP6?
More memory 4Gb/FPGA(total of 20Gb)
Clocks and controls

8. Difficulties Hard to have a design with all chip advances
Has to make a compromise
Frame
Board room
DDR3 support by FPGA
Bandwidth limit with SFP/SFP+
AMC width to DDR3
Layout
14 layers
Through holes
Both sides

9. New version Which Platform ---------XTCA
ATCA or XTCA
ATCA or ATCA Carrier + AMC
3.125Gbps/ch or 6.25Gbps/ch -
6G/FPGA
2 X 3Gbps/link
DDR2 or DDR3 or DDR4, or ……  2X DDR2
V4 or V5 or V6 or SP6?  V5
More memory 4G/FPGA(total of 20Gb)->4(20)G
Clocks and controls Yes

10. Motherboard/Carrier Board
4 AMC connectors
FPGA0 for interconnections in XTCA V4
IPMC routing
Clock/trigger/ distributions
Power conversions
RTM reservation

11. Daughter Board/AMC
2 x 3Gbps /FPGA
2 x 2G DDR2
1 Gbps ethernet
1 UART

12. AMC: Component side 2 x SFP+ 1 ethernet 1 UART(on board) FPGA 2 DDR2
IPMC
AMC connector

13. AMC: Soldering side
Powers
FLASHs

14. Appearance

15. Other option from Soeren(2G)
2G/FPGA DDR2
SFP+ socket
Virtex-4 grade 11
Based on V2+ PCB

16. Short plan
Dec first prototype
Thanks!

17. backups